VISION AND STRATEGY
The vision of the mechanical design research area is to develop up-front mechanical design tools with user interface for IC-package-system design for reliability. The strategy includes modeling and design for (i) process induced residual stresses and defects (ii) designing against component-level failure mechanisms (iii) designing against system-level failure mechanisms and (iv) quantifying the effect of component-level mechanical failures on system-level functionality through multi-physics models.
CURRENT RESEARCH FOCUS
1. Mechanical Design of Through Package Via (TPV) in Glass and Silicon Substrates
Mechanical design guidelines are being developed by modeling and reliability characterization of TPVs and RDL layers in low CTE glass and silicon substrates to address low-stress packaging of 3D-ICs with TSV and ULK on-chip ILD.
2. TSV Modeling, Design and Reliability Characterization
This project, funded by SRC, focuses on physics based modeling of various material, geometry and process effects on high aspect ratio TSV structures and thermal cycle reliability testing based validation of the models. Various geometries such as circular, square, annular and coaxial TSVs of varying diameter and depth are being modeled, fabricated and tested.
3. Mechanical Design of First Level Interconnections: Cu-to-Cu Adhesive Bonding
Copper has shown excellent prospects for replacing solder technology in next generation chip-package interconnects owing to its excellent electrical conductivity and mechanical stability. The research in this area at PRC is focused on exploring highly reliable direct Cu-to-Cu interconnections bonded at low temperature.
4. Microscale Plasticity and Mechanical Design of Microvia Structures
Materials display strong scale effects when the characteristic length scale associated with non-uniform plastic deformation is on the order of microns. The classical plasticity theories cannot predict the size dependence of material behavior at the micron scale because their constitutive models typically possess no internal length scale. The focus of this research project is on material length scale effects on plastic deformation and fatigue of microvia structures, with particular emphasis on small via diameters below 25um and high aspect ratio vias.
5. Novel Large Area Composite Substrates for High-Density and High Reliability Packaging
This research funded over a period of seven years by NIST and ARL involves the exploration, development and evaluation of novel large-area Silicon Carbide (SiC) based composites for packages and PWBs. This family of materials has the processability benefits of large-area organic substrates while retaining high stiffness (>200 GPa) and Si-matched CTE (~ 3 ppm/°C).
INDUSTRY CONSORTIA WITH MECHANCIAL DESIGN RESEARCH
1. Embedded MEMS, Actives and Passives (EMAP)
2. Silicon and Glass Interposer (SiGI)
SELECTED PUBLICATIONS
1. K. Tunga and S. K. Sitaraman. 2007. An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls.
Transactions of the ASME – Journal of Electronic Packaging 129, 427-433.
2.K. Kacker, et al. 2007. A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance. Transactions of the ASME – Journal of Electronic Packaging 129, 460-468.
3. Kumbhat, N., et al “Novel Ceramic Composite Substrate Materials for High-Density and High Reliability Packaging,” IEEE Transactions on Advanced Packaging, Vol.30 (4), 2007, pp 641-653.
4. R. V. Pucha, et al. 2004. Materials and Mechanics Challenges in SOP-Based Convergent Microsystems. Micromaterials and Nanomaterials, A publication series of the Micro Materials Center Berlin at the Fraunhofer Institute IZM, 3, 16-29.
5. R. V. Pucha, G. Ramakrishna, S. Mahalingam and S. K. Sitaraman. 2004. Modeling Spatial Strain Gradient Effects in Thermo-Mechanical Fatigue of Copper Micro-structures. International Journal of Fatigue 26(9), 947-957.
RECENT INVENTIONS
1. Multi-Axis Compliance Spring, U.S. Patent 7,011,530, Suresh K. Sitaraman, Lunyu Ma and Qi Zhu, March 14, 2006.
2. Compliant Off-Chip Interconnected, U.S. Patent No. 6,784,378, Suresh K. Sitaraman, Qi Zhu and Lunyu Ma, August 31, 2004