VISION AND STRATEGY
Electrical modeling, tools and design for ultra-miniaturized, SOP-based packages, modules and systems is the focus of this core area. The electrical design is aimed at a wide-range of packaging technologies such as organic, glass and silicon.
CURRENT RESEARCH FOCUS
1. Organic Package
Electrical design of ultra-miniaturized and high density organic packages with chip-last Embedded MEMS, Actives and Passives (EMAP). EMAP technology involves embedding active chips within cavities and thin film passives in build-up and multilayer organic substrates using low cost manufacturable approaches. The actives include multiple embedded Digital, Analog, RF, and MEMS ICs, and IPDs.
A. High Frequency Materials Characterization
New methods of extracting dielectric properties of thin polymer films over a range of frequencies from DC to 110 GHz have been explored and demonstrated which include effects such as thickness variation, surface roughness and via parasitics. This project is in partnership with SAMEER, India.
B. Design of Ultra-Thin Package with Embedded Digital and RF ICs in Cavities
Aims at a new and improved packaging technology that can lead systems with increased functionality and further reduced form factor than the state of the art. This research project addresses electromagnetic coupling and shielding issues in the integration of mixed signal ICs and components by chip-last and chip-first embedding and 3D stacked packages.
C. High Quality Factor Embedded RF Passives
A new low loss and low moisture organic substrate material system has been demonstrated combining thin glass-reinforced polymer laminates and thin build-up films with stable dielectric properties in the DC – 110 GHz range. Embedded LC filters with insertion loss of <1 dB at 2.4 and 5.8 GHz bands have been demonstrated. A new series of low loss dielectric materials with dielectric constant ranging from 7-10 are also being explored for embedding ultra-low profile filters and RF passives.
D. Functional Module Demonstrators
This task includes the demonstration of a functional module with a high I/O digital/mixed signal chip embedded within a cavity in a multilayer organic package. In addition to demonstrating the feasibility of embedding multiple chips within a single package, the effects of electromagnetic interference between the chip and the package will also be analyzed.
2. Silicon and Glass Package
The electrical design of low-cost silicon and glass packages to package 3D ICs focuses on the development of high-performance and ultra-miniaturized packages with highest Through-Package-Via (TPV) and I/O density.
A. Design of Interconnects
The glass and silicon packages are being designed for best signal performance for digital and RF applications. The electrical design and test focuses on three elements: first level interconnects, re-distribution wiring layers, and TPVs.
B. Materials and Structure Characterization
The key parameters being characterized are interconnection yield, and signal transmission speed and loss. Materials and structure characterization in Phase 1 includes 1) dielectric constant and loss tangent of package substrate, insulator and liner, and 2) R, L, G, C and, Z0 of traces and TPVs in the interposer.
C. Novel Designs for Silicon Packages
The MOS capacitance effect associated with a through via in silicon packages has been rigorously studied and modeled. Novel electrical designs for power, signal and clock distribution in 3D silicon packages are being developed, utilizing this effect.
D. High Quality Factor Embedded Filters in Glass Substrates
High Quality Factor embedded RF filters and other passives are designed on a stackup consisting of glass core with buildup layers on top and bottom. The glass consists of through package vias (TPV). The key goal is to achieve high electrical performance comparable to organic substrates, with the highest I/O density, comparable to silicon.
E. Glass and Silicon Package Demonstrator
The entire glass and silicon Package will be designed, modeled, simulated and characterized. Other tasks that will be carried out in the two-year Phase I program are model to hardware correlation and development of electrical design guidelines. Key deliverables of the electrical design effort will include a set of design rules for glass and Si packages as well as electrical models for designing the package to the research targets.
3. 3D ICs and Systems
The main research focus is on physical design for 3D IC/SiP/SOP, microarchitectural floorplanning, and FPAA (field programmable analog array).
- Physical Design Automation for Fast and Reliable 3D Circuits
- Co-Optimization and Limit Study of Thermal, Power, Clock, and Signal Distribution Networks in 3D ICs
- Design, Fabrication, and Testing of 3D-MAPS: A Massively Parallel Processor with 3D Stacked Memory
- 3D Integration of Sub-Threshold Multi-core Co-processor for Ultra Lower Power Computing
- A Digital Infomedia System - Immersive Technologies on a Hybrid GPU-CPU Platform
- Design for Manufacturing Issues with Through-Silicon-Via
- Design of 3D Integrated Heterogeneous Systems
- Design for Manufacturability of 3D ICs with Through Silicon Vias
INDUSTRY CONSORTIA WITH ELECTRICAL DESIGN RESEARCH
1. Embedded MEMS, Actives and Passives (EMAP)
2. Silicon and Glass Interposer (SiGI)
3. Mixed Signal Design Tools (MSDT)
4. 60 GHz Module Design and Test (60G)
SELECTED PUBLICATIONS
1. V. Sridharan, S. Min, V. Sundaram, V. Sukumaran, S. Hwang, H. Chan, F. Liu, C. Nopper and, R. Tummala, “Design and Fabrication of Bandpass Filters in Glass Interposer with Through-Package-Vias (TPV),” IEEE ECTC Conference. Las Vegas, NV. June 2010.
2. S. Min, S. Hwang, D. Chung, M. Swaminathan, V. Sridharan, H. Chan, F. Liu, V. Sundaram and, R.R. Tummala, "Filter integration in ultra thin organic substrate via 3D stitched capacitor," Electrical Design of Advanced Packaging & Systems Symposium, 2009. (EDAPS 2009). pp. 1-4, 2-4 Dec. 2009.
3. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, & R. Tummala, “Electrical Modeling of Annular and Co-axial TSVs Considering MOS Capacitance Effects,” IEEE Electrical Performance of Electronic Packaging and Systems Conference (EPEPS). Portland, OR. October 2009.
4. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, & R. Tummala, “Electrical Modeling of Through Silicon and Package Vias,” IEEE International Conference on 3D System Integration (3D IC). San Francisco, CA. September 2009.
5. T. Bandyopadhyay, L. Shan, Y. Kwark, X. Gu, M. Ritter, C. Baks, R. John, & R. Tummala, “A Study on Crosstalk Analysis in Aggregative Transmission Lines with Turning Vias,” IEEE ECTC Conference. San Diego, CA. May 2009.
6. Sung Kyu Lim, "Physical Design for 3D System-On-Package: Challenges and Opportunities," IEEE Design & Test of Computers, Vol. 22, No. 6, pp. 532-539, 2005.
RECENT INVENTIONS
1. V. Sundaram, F. Liu, R. Tummala, V. Sukumaran, V. Sridharan, Q. Chen, “Novel through Package via (TPV) Structures on Glass Interposer and Methods for Fabricating the Same”, Invention Disclosure, Feb 2010.