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Interconnections, Assembly and Reliability

Prof. Rao R. Tummala

Mr. Nitesh Kumbhat

Dr. Raj Pulugurtha


Ultra-miniaturized, highly-reliable, fine-pitch and low-cost device to package to system interconnections with particular focus on electrical and mechanical design, advanced thin-film materials and processes, assembly and reliability.


1. Copper-to-Copper Interconnections with Adhesives
The goal of this research is to explore and demonstrate the most leading-edge, highly-reliable, ultra-fine pitch (~30µm) Chip-to-package Cu-Cu interconnection at low temperatures. (160°C)

2. Reactive Nano-Particle Based Pad-to-Pad Interconnections
The objective of this project is to enable extremely fine-pitch pad-to-pad interconnections usingultrathin “bumpless” nano-copper as the reactive bonding layer. The nano-copper layer enhances the reactivity between the copper bump on IC and the pads on the substrate, thus lowering the bonding temperature.

3. Nano-Composite Solder Based Interconnections
The objectives of this project are to explore novel indium-based nanocomposite interconnections that can be assembled at temperatures less than 175°C and to demonstrate the thermo-mechanical reliability and electromigration resistance requirements for such solders at fine pitch.

4. Silicon and Glass Package to PWB Interconnections
The objective addresses the biggest barrier to the use of Silicon and glass packages since their TCE is very low (3PPM) compared to 17 PPM for organic board. This project aims to design, fabricate and test SMT-compatible package to board interconnections to achieve high thermo-mechanical reliability, despite high CTE mismatch between large glass or Si packages to traditional PWB.

5. Novel Capillary and Wafer Level Underfills: The objective of this project is to explore novel capillary and wafer level underfills for area-array interconnections to achieve high yield and reliability with halogen-free packages.

6. Zero-Stress Interconnections: The objective of this project is to explore industry infrastructure-friendly, novel and scalable interconnection architectures to achieve high reliability and reworkability at low cost.


1. Embedded MEMS, Actives and Passives (EMAP)
2. Silicon and Glass Interposer (SiGI)


1. Abhishek Choudhury et al, Accepted for Electronic Components and Technology Conference, 2010
2. Rao Tummala et al, Chip-Last Interconnection to Thin Organic Packages with Advanced Dilectrics and Fine Pitch IOs, Proceedings, Proceedings, Pan Pacific Microelectronics Symposium, 2010
3. Rao Tummala et al, Proceedings, Custom Integrated Circuits Conference, 2009, pp. 439-444
4. Nitesh Kumbhat et al, Proceedings, Electronic Components and Technology Conference, 2009, pp. 1479-1485


1. High aspect ratio metal-polymer composite structures for nanointerconnects, US Patent # 7,262, 075, October 2007
2. Lead-free bonding systems, US Patent # 7,5556,189 B2, July 7, 2009
3. High aspect ratio metal polymer composite structures for nanointerconnects, US Patent # 7,557,448 B2, July 7, 2009