Technology Alliances
Digital Packaging, Microvia and Global Interconnect, Embedded Optoelectronics,

SOP Design Technology, RF Packaging, Thermal Management, Wafer Level Packaging
Embedded Optoelectronic Interfaces and Interconnections

Industry's Strategic Need back

Board, substrate, and chip interconnections are facing critical interconnections limitations as channel and aggregate data rates rise. Optical interconnections embedded into boards, substrates, and chips can offer high performance interconnections for clock and critical data paths. Critical issues that face designers include materials, fabrication, and integration choices for waveguides, beam steering elements, emitter and detector components, and interface electronics. There also exists a significant gap in modeling, and design tools for the co-optimization of optoelectronic components and interface circuits, as well as for the co-optimization of electrical and optical interconnections on the same substrate. Finally, design for yield using alignment-tolerant design techniques is critical for performance and cost control as speeds increase to hundreds of Gbps per channel and aggregate rates of tens of Tbps.

The Packaging Research Center at the Georgia Institute of Technology (GIT) is initiating a technology alliance to design, fabricate, and test optoelectronic interconnections and interfaces, which are embedded in electrical interconnection substrates. This Alliance seeks to integrate low cost, alignment-tolerant waveguide optical interconnections into electrical interconnection substrates, which include FR4, polymer, ceramic, and silicon. Waveguides, beam steering elements, emitter and detector conversion interfaces. Interface electronic circuits will all be built to study complete links. Analysis of combined electrical/optical interconnect design optimization for specific application areas will be emphasized. Companies who participate in this alliance will receive modeling and design, materials and process, testing and optimization knowledge.
 
 
schematic graphic

opto interface grapic 1
opto interface graphic 2
 

 

Research Directions back
 
This Alliance is integrating embedded optical interconnections into standard electrical interconnection boards, substrates, and chips, including FR4, polymer, ceramic, and Si. These optical interconnections are created using deposited waveguides (with a focus on organics, and some research on inorganics), thin film active optoelectronic devices (emitters, detectors), embedded optical passive elements (gratings, mirrors), and foundry interface integrated circuits. Two versions of embedded substrates are in fabrication: with electrical output from the substrate using embedded emitters and/or detectors, and with optical outputs from the substrate using beam turning elements. The optical substrate can be fully tested before chip assembly, and can be designed with exclusively electrical I/Os, or can be fiber coupled.
 
Specific Technology Goals back

1. 1-100 Gbps/channel integrated optical substrate with PDs
2. 100 Gbps - 16 Tbps aggregate integrated optical substrate with PDs with SDM, WDM
3. 1-10 Gbps/ch integrated optical substrate with PDs and Receivers (TIAs)
4. Study of latency and skew for optical and electrical interconnections
5. Co-optimization of OE components and interface electronics
6. High performance alignment-tolerant designs for OE interfaces

Integrated Testbed and Deliverables back

1. Fabricate embedded optical interconnections using organic waveguides with optical signal
evanescently coupled into photodetector embedded into waveguide for FR4, ceramic, silicon.
2. Fabricate embedded optical interconnection using organic waveguide with optical signals coupled into and/or out of the substrate using grating couplers.
3. Evaluate competing waveguide and interface materials and fabrication technologies for high performance, low cost optical signal distribution.

Recent PRC Advances back

1. Demonstrated embedded optical waveguides with PDs at 1 Gbps
2. Demonstrated 9.8 ps FWHM thin film I-MSM PDs
3. Demonstrated 1.2 Gbps integrated Si CMOS PD/TIA

PRC Research Facilities back

1. Microelectronics Research Center cleanroom facilities
2. Optical characterization, including electro-optic sampling to over 500 GHz
3. Optoelectronic/electronic test lab
4. PRC prototype lab
5. Next-generation substrate lab

 

Research Focus back Research Team back E-Mail Address back
  • Optoelectronic waveguides, passives, devices, and integration
Prof. Gee-Kung Chang

geekung.chang@ece.gatech.edu

 
  • Optoelectronic device material design and growth

 
 
  • Fundamental optical grating design and development
Prof. Tom Gaylord tom.gaylord@ece.gatech.edu
 
  • Electrical/optical signal co-optimization and CAD
Prof. Abhijit Chatterjee

abhijit.chatterjee@ece.gatech.edu

  • Board level opto
Prof. R. Tummala
Prof. Fuhan Liu
rtummala@ee.gatech.edu
fliu@ee.gatech.edu
 

Dr. Daniel Guidotti

Lixi Wan

 

Contact for Additional Information back

Professor Gee-Kung Chang
Byers Eminent Scholar Chair in Optical Networking
School of Electrical and Computer Engineering
Optics and Photonics, and Telecommunications
Phone: 404.385.2712
Fax: 404.894.8363
Office: Cent 5120
geekung.chang@ece.gatech.edu


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