Core Research Areas

VISION AND STRATEGY

3D Systems by System-on-Package (SOP) Research Concept
The research vision is to explore and demonstrate new fundamental concepts in all the core technologies necessary to achieve highest functionality at smallest size and lowest cost for electronic and bio-electronic 3D systems by embedded thin film components and high density interconnections at nanoscale, combining the best of IC, package and system integration as shown in the figure below.

The PRC’s strategy is to explore new electrical, mechanical, thermal designs, nano-materials and process integration concepts in two packaging technology platforms, organic and inorganic using silicon or glass wafer-level packages. It is also PRC’s strategy to demonstrate leading-edge packaging innovations on 300mm panels at Georgia Tech, to be scaled up further to 600 mm or so panel sizes by package manufacturers by involving supply chain partners in materials and tools, to commercialize the two platform technologies. The research programs are divided into seven fundamental core areas with interdisciplinary teams of academic faculty, students, research faculty and industry mentors, with a set of focused research targets as described below.


7 CORE RESEARCH AREAS

1. ELECTRICAL DESIGN
Research Focus: Signal integrity and power delivery network, embedded actives design and test, high Q RF passives and antennas, embedded decoupling capacitors and high density inductors, TSV and TPV modeling and characterization, CAD and design tools, 3D-IC routing and design, digital/RF/analog/power module design for DC-110GHz applications, 3D systems design.

    Research Targets:
  • 10-100Gbps per channel data rates







2. MECHANICAL DESIGN
Research Focus: Thermo-mechanical modeling, virtual reliability prediction, TSV stress and reliability, interfacial stress and delamination, low K/ELK/ULK ILD cracking, nano-indentation and mechanical property characterization, nano-scale mechanical modeling, embedded actives and passives reliability.

    Research Targets:
  • JEDEC standards for temp cycling >1000 cycles (-55°C to 125°C), HAST, 85/85 with bias
  • IPC standards for CAF and SIR






3. NANOMATERIALS
Research Focus: High dielectric and high permeability nano-composites and thin film materials, Sol-gel precursors and synthesis for nano-scale thin films, nano-ACF and NCF adhesives for interconnections and bonding, nanocomposite underfills, CNT based interconnection and thermal interface materials, ALD and nano-scale thin film processes for high density components.

    Research Targets:
  • Film thickness - 10-500nm
  • Particle size - <100nm
  • Process compatibility - Organic and silicon/glass substrates
  • Process Temperatures – <200°C (Organic), <400°C (Si and glass)
  • Dielectric Constant - 2.5-3.5 (low K), 7-100 (RF high K), >1000 (high K)
  • Dielectric Loss - <0.005

4. NANOCOMPONENTS
Research Focus: High density capacitors, low TCC and high Q RF capacitors, high density inductors for power conversion, high Q RF inductors, filters & antennas, low TCR & thin film resistors, supercapacitors and thin film batteries.

    Research Targets:
  • Capacitance density - 5-100µF/cm2
  • Magnetic Permeability - 10-100 up to 1 GHz
  • RF Passives Quality Factor - >200 (1-110GHz)







5. INTERCONNECTIONS, ASSEMBLY, & RELIABILITY
Research Focus: Cu-to-Cu low temperature bonding with adhesives, low temperature and ultra-fine pitch metallurgical bonding for Cu interconnections, underfill processes for low stand-off, chip-last embedded IC interconnections, highly reliable second level interconnections for low CTE packages, nano-structured interconnections.

    Research Targets:
  • Chip-to-Package I/O pitch – 10-50µm array
  • Bonding Temperature – <200°C
  • Package-to-PWB I/O Pitch – 300-500µm








6. THERMAL TECHNOLOGIES
Research Focus: Thermal modeling, single and dual phase cooling, microjet and microchannel coolers, thermal interface materials, thermal characterization of packages and systems.


Research Targets:

  • Heat Dissipation – 100W/cm2 and higher
  • RTIM - <0.005 °C cm2/W





7. SYSTEMS INTEGRATION
Research Focus: Ultra-thin organic substrates with 5-10µm design rules, low loss organic substrates for DC-110GHz, high Dk and low loss substrates, large panel Silicon and glass substrates, low cost 1-5µm lines on Silicon and glass substrates, low cost 10-30µm diameter TPVs, Digital and RF modules with embedded actives and passives, MEMS and sensor packaging with low moisture uptake and hermetic coatings.

    Research Targets:
  • Substrates
    • Dielectric Thickness - 5-10µm (dry film)
    • Conductor Thickness - 3-10µm (Cu)
    • Conductor Feature width - 3-10µm
    • Through package via (TPV) - 10-25µm diameter, 25-100µm pitch
    • Microvia - 10-25µm diameter, 25-50µm pitch
    • Number of Build-up layers - 2-4 (double sided)
  • Modules and Systems
    • Package or Module Thickness - <500µm
    • Function Integration: Digital, RF, Analog, MEMS, Sensors, Bio
    • Bandwidth: >10GB/s per channel