| Facilities
and Equipment
PRC's
Laboratory Vision & Mission
The PRC seeks to explore new research frontiers, to challenge
their feasibility through cross-disciplinary test vehicles and to transform
these leading-edge, next-generation technologies into functional SOP
prototypes. Our world class facilities are uniquely designed to support
the full range of our research activities.
The Center's research program provides unique opportunities for students, professors
and industry engineers to work collaboratively on cross-disciplinary projects
ranging from fundamental to system-level prototypes. These activities are supported
by a comprehensive, three-tiered system of research laboratories. The first tier
laboratories involves the Fundamental Research
Laboratories which enable and support fundamental discovery research. These
facilities are located within the building of the home departments of the principal
investigators. The second tier facility is the Microelectronics Research
Center, used for the the small area integration of fundamental research discoveries
into small area test vehicles. The third and final tier laboratories are the Prototype Research
Laboratories. These facilities enable students and industry to demonstrate
new technologies as well as the low cost, high performance, and high reliability
characteristics of these leading-edge technological innovations by utilizing
proof-of-concept system prototypes.
Facilities
Used for Fundamental Research back
The PRC seeks to explore new research frontiers and to enable
the development of fundamental research discoveries. The PRC supports
several fundamental research laboratories, which are located across the
campus of the Georgia Institute of Technology. The principal investigating
professors manage these first tier laboratories. Our world-class facilities
are uniquely designed to support the full range of fundamental research
and support all aspects of the microelectronics packaging at the system
level.
Small
Area Integration Lab (Microelectronics Research Center) back
This lab supports the successive integration of fundamental
research discoveries into multidisciplinary, alliance-level, small area
test vehicles, which are used to validate research results and to demonstrate
process integration of fundamental research projects. This research
facility, located in the Microelectronics Research Center (MiRC) on
the Georgia Tech campus, is a 7,000 square foot class 1000-100 clean
room facility. It is here that researchers demonstrate the ability to
integrate fundamental research innovations for Optoelectornics, Integral
Passives, and Low Cost High Density Wiring processes on a small-scale
basis prior to implementation in large-area prototypes. This lab includes:
- Plasma Enhanced
Chemical Vapor Deposition
- Electron
Beam Evaporator
- Filament
Evaporator
- Programmable
Rapid Thermal Processor
- Scanning
Electron Microscope
- Auto-load
and Manual Spin Coater
- Spin Develop
Station
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- Mask Aligner/UV
Exposure Tool
- Automated
Dicing Saw
- Polishing
and Lapping Stations
- Wire Bonders
(Au,Cu,Al)
- Dark Room
Facility for Mask Generation
- RF & DC
Magnetron Sputtering Systems
- Reactive
Ion Etch Chambers
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Prototype Research Labs back
These laboratories enable the Center to demonstrate new technologies
as well as low cost, high performance, and high reliability characteristics
of leading-edge technological innovations by utilizing proof-of-concept
system level test vehicles. This grouping of laboratories consist of
the Package Design Laboratory,
the SOP Substrate Fabrication Laboratory, and the SOP Module Assembly Laboratory.
Together, these laboratories provide a total of 17,850 square feet of
laboratory space dedicated to large area, next-generation prototype research.
Additionally, these laboratories are the key-differentiating factor separating
the PRC from other traditional academic research programs. It is in these
laboratories that the results of fundamental research efforts are integrated
into cross-disciplinary, functional sub-systems, or system level, proof-of-concept
prototypes. In addition to this critical research validation, these laboratories
provide opportunities not elsewhere available for practical, hands-on
education for students and for industry engineers.
SOP
Packaging Design Lab back
This facility consists of 3,500 square feet of laboratory space
used for the design of high performance packages and interconnects. . Managed
by Dr. M. Swaminathan tools include Microwave CAD Tools, Design Workstations,
Cascade Substrate Probe Station, A cluster of SUN workstations with CAD
software for the physical design, modeling, analysis, and simulation
of packages. In addition, the facility also supports high speed, time-domain
measurement equipment for the characterization of interconnects and packages
with 50 GHz Digital O-Scope, 20Ghz Sampling Heads, LCR Meter, High Speed
Pulse Generator, Impulse Forming Network Analysers.
SOP
Substrate Fabrication back
This lab began operating in March 1997 and is a class 1,000
clean room maintained at 68F and relative humidity of 35 percent. This
prototype research laboratory enables the processing of 300 mm substrates
with High Density Wiring (HDW) and integral passives. Process capabilities
in this laboratory include substrate cleaning and preparation, polymer
deposition of wet films by either spin or meniscus coating, polymer deposition
of dry films, soft bake and final film curing, full field photolithography
and laser ablation for feature development, and feature inspection and
measurement, both electrolytic and electroless plating electrolytic
copper gold, nickel and solder, which will enable metalization of substrates
to the parameters defined in PRC's research program. Equipment includes:
SOP
Module Substrate Lab back
The Next-generation SOP Module Assembly Laboratory provides a class
100,000 to class 10,000 environment enabling the research and process
integration needed to assemble functional sub-system test vehicles. In
this laboratory, substrates processed in the SOP Substrate Fabrication
are interconnect tested and flip-chip assembled into a complete sub-system
prior to thermal cooling assembly and reliability testing. Current process
capabilities of this facility include precision stencil printing, plasma
substrate cleaning, high speed precision flip-chip placement, SMT component
placement, component placement inspection via X-ray, chip to substrate
connection via reflow of eutectic solders or conductive adhesives, underfill
dispense, air-to-air thermal shock, temperature/humidity/bias testing,
as well as substrate interconnect and functional module electrical testing,
and material or process characterization. Enhancements underway include
the addition of substrate dicing, rework station, HAST, and liquid-to-liquid
thermal shock. This lab includes:
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