Microsystems Packaging Research Center

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Technology Alliances
Digital Packaging, Microvia and Global Interconnect, Embedded Optoelectronics,
SOP Design Technology, RF Packaging, Thermal Management, Wafer Level Packaging

Digital Packaging Design

Industry's Strategic Need back

Maintaining signal integrity represents one of the major bottlenecks for enabling reliable mixed signal systems. This is due to the increase in speed, reduction in voltage, increase in power, and the integration of mixed signal functions. Examples of such systems include electro-optic USB interfaces, wireless transceivers, wireless access networks, mobile computers, server farms and other high speed computing applications. Due to the fast transition of digital signals, the analog behavior of these signals becomes very important. Issues such as cross talk, reflections, switching noise, eye patterns and delay therefore have to be addressed. In addition, isolation between the digital and analog circuits is required. Power integrity, similarly, is a major challenge. This challenge is a result of the high power consumption of future microprocessors, which require a low impedance power distribution network over a large frequency bandwidth. In addition, in mixed signal systems, a major mode of coupling is through the power distribution network. The combination of wafer level packaging and multifunction SOP board technology has many advantages for the design of digital systems with mixed signal interfaces. The wafer level package reduces parasitic's through short compliant and rigid leads, improves isolation by separating incompatible circuitry and enables much better matching of components for developing integrated solutions.

Eye Diagram for Digital Systems with
a Random Binary Source

Research Directions back

Power Integrity

Chip-Package Co-design methodologies for
system partitioning
Design of the transitions from the chip into the
high-density substrate for supporting high
currents and fast transition rates
Electromagnetic radiation and compatibility
Design of the organic substrate for supporting
>200W of power for high frequency
microprocessors
Design of embedded circuits in the organic
substrate such as AC blocking filters, decoupling
and matching networks

Signal Integrity

Design of clock distribution networks - both electrical and optical
Development of mixed signal and digital design tools

Integrated Testbed and Deliverables back

This alliance will consist of a high-speed digital test bed with RF and Optical interfaces. The goal of this test bed is to demonstrate >1Tb/s of signal throughput in the SOP board and mixed signal interfaces for converting the signal into either RF or Optical form. The mixed signal interface activity will be performed with the RF and Optical alliances. The alliance will also be involved in two other testbeds-with the design and fabrication of the global and micro via testbed and with the wafer level packaging testbed

Recent PRC Advances back

Modeling and measurement of the power delivery system for a 750MHz SUN microprocessor switching 400 interconnects and a high speed image processing board from Kodak. Design tools based on the cavity resonator method, FDTD, transmission matrix, BEMP and GTLE methods have been developed. These have been applied to complex test boards from SUN, IBM and Kodak.
Accurate simulation of the eye patterns of digital systems through extracted models from TDR measurements. This has a much higher accuracy than standard W-Element models and is ideally suited for the simulation of >5Gb/s signals.

Selected Publications back

J. H. Kim and M. Swaminathan, "Modeling of Irregular Shaped Power Distribution Planes using the Transmission Matrix Method", IEEE Transactions on Advanced Packaging, Vol. 24, No. 3, pp. 334-346, Aug. 2001.
J. Cong and S. K. Lim, "Physical Planning with Retiming", IEEE International Conference on Computer Aided Design, p2-7, 2000.
W. Woo, L. Ding, G. T. Zhou, and J.S. Kenney, "An RF/DSP Test Bed for Baseband Pre-Distortion of RF Power Amplifiers," 57th Automatic RF Testing Group Conf. Dig., pp. 54-70, Phoenix, AZ, May 25, 2001.

Facilities back

Facilities available include an SOP design laboratory and an SOP measurement laboratory with both transmission and radiation measurement capabilities.

Measurement Laboratory

Research Focus back	Research Team	E-Mail Address
Digital design, power distribution, RF design, electrical characterization, modeling and simulation	Prof. M. Swaminathan, Alliance Leader	mahadavan.swaminathan@ee.gatech.edu lixi.wan@ece.gatech.edu
Mixed signal design, system architecture	Prof. James S. Kenney	james.kenney@ece.gatech.edu
Digital design, GSI, physical design and routing	Prof. Sung-Kyu Lim	sungkyu.lim@ece.gatech.edu
System architectures	Prof. Vincent Mooney	vincent.mooney@ece.gatech.edu
Microvia and global interconnect	Prof. Rao Tummala Dr. George White Mr. Venky Sundaram	rtummala@ee.gatech.edu georgew@ee.gatech.edu vsunda@ee.gatech.edu
Wafer level packaging	Prof. C.P. Wong	cp.wong@mse.gatech.edu
Parasitic Extraction, Electromagnetic Modeling	Prof. Andrew Peterson	andy.peterson@ee.gatech.edu

Industry Partners and Sponsor back

Sun Microsystems, Rambus, IBM, AMD, HRL, Cadence, SRC, DARPA

Contact for Additional Information back

Prof. Madhavan Swaminathan - Digital Alliance Leader - Packaging Research Center
Professor - Electrical & Computer Engr (M/C 0250)
Tel (404) 894-0514
E-Mail: madhavan.swaminathan@ee.gatech.edu