Georgia Institute of Technology Packaging Research Center An NSF Engineering Research Center Leading the SOP & Nano Packaging Revolution
	e-newsletter Vol. 1, Issue 1 – April 2003

P²ES - A Novel Stacked Microvia Technology Innovation
A novel technology that involves panel plating and subsequent etching of studs to form stacked microvias on printed wiring boards is being developed at the Packaging Research Center. The process by which these structures are fabricated allows for the realization of uniform height stacked via structures in the absence of costly planarization processes such as chemical mechanical polishing, typically employed in a multi-layer stacked structure. The panel plated etched stud process, termed P²ES, can be used to enable both System-on-Package (SOP) and System-in-Package (SIP) applications.

Stacked via structures offer the highest wiring capability and improved electrical and thermal performance over traditional conformal microvias used in today’s high-density interconnect (HDI) boards. The advantages of the P2ES is the use of cost effective methodologies to fabricate copper studs with uniform height across a large area and the use of standardized etching processes that are commonly practiced in the printed circuit board industry. The P2ES process has been demonstrated on 12”x12” FR-4 boards with less than 1 micron variation on panel plated copper thickness. For further information, please contact Fuhan Liu (fliu@ee.gatech.edu), George White (georgew@ee.gatech.edu), Venky Sundaram (vsunda@ee.gatech.edu) or Rao Tummala (memount@ece.gatech.edu).

100 Micron Pitch Lead-Free Solder Bumping Process
The PRC has begun to develop a wafer level 100 micron pitch, 32-micron high lead-free solder (Sn3.5Ag0.5Cu) bumping process using Super Solder paste technology. The chip is designed as a periphery flip chip array (20 x 20mm) with 2976 I/O’s by PRC’s Singapore Partner, IME. For further information, please contact Doraiswami Ravi (dravi@ee.gatech.edu)

Highest Q Inductors in Organic Substrates
The PRC develops unique designs and processes to fabricate inductors with the highest Q factors in the industry, with quality factors in the range of 60-180 at frequencies in the 1-3 GHz range with inductances in the range of 1nH to 20nH. These inductors were fabricated on an organic substrate using a low-cost, low-temperature (<150°C) laminate batch fabrication process. This is the first demonstration of such high Q inductors in organic substrates. The microstrip loop and spiral inductors with areas <4.5mm² and volumes <3mm³ are ideally suited for integration in compact RF/microwave systems. For further information, please contact Madhavan Swaminathan (madhavan.swaminathan@ee.gatech.edu), Rao Tummala (memount@ece.gatech.edu), Joy Laskar (joy.laskar@ee.gatech.edu), or Manos Tentzeris (etentze@ece.gatech.edu).

Embedded RF Packaging
The RF/wireless team has led the development of a hybrid electromagnetic and mechanical full-wave time-domain simulator that can be used for the efficient modeling of 3D integrated RF modules (cellular, WLAN 802.11x, LMDS) as well as of the transient and steady-state of packaged RF MEMS. In addition, it developed models for materials such as low temperature ceramics and organics that can be used for multilayer SOP-based transceivers. Transmission lines, filters, 2D/3D passives and packaging-adaptive antennas have been already designed for these type of materials. For further information, please contact Prof. Manos M. Tentzeris (etentze@ece.gatech.edu).

Partnerships

The PRC Successfully Completes its First IAB Meeting of the Year
This year's IAB meeting, held on February 25th and 26th, proved to be a great success, and attendance was high despite the economy and heightened airport security measures. The event was preceded by two short courses presented by Prof. Paul Kohl and Dr. Kevin Martin, who presented "Chip Scale Packaging,” and Dr. Stephane Pinel who presented “RF/Wireless Packaging: Status and Challenges." Both courses offered a wealth of information for first time attendees.

An orientation for new members was presented by PRC Director Rao R. Tummala. It was an informative overview of the PRC's SOP vision, its accomplishments in research, education and industry collaboration with the microelectronics community. Next, he conveyed his vision to move to nanosystems by means of nano-packaging. He then moved to and welcomed all the IAB members, covered meeting objectives, reviewed the most recent NSF site visit. Carl Rust subsequently presented the proposed new membership and alliance structure.

The other sessions focused on Technology Alliance overviews as well as detailed research discussions in all 7 technology alliances. These were followed by student poster reviews and selection of best poster awards. For further information, contact Reed Crouch (reed.crouch@ece.gatech.edu), Mary Ellen Mount (memount@ece.gatech.edu), or Angie Hughes (angieh@ee.gatech.edu)

PRC Announces Next Industry Advisory Board Meeting
The next Industrial Advisory Board Meeting of the Packaging Research Center will be held September 23-25, 2003 on campus at Georgia Tech in Atlanta, Georgia. The meeting will consist of short courses on System-on-Package (SOP) topics, review of PRC research activities, and mini-consortia working group meetings on specific technology areas. Only PRC members may attend. For additional information on PRC membership, please contact PRC Associate Director, Carl Rust (carl.rust@ee.gatech.edu), 404-894-3843.

Education

The PRC Continues to Produce Top-Notch Students for the Industry
In the past eight years, Georgia Tech PRC has graduated a total of 391 students with specialization in Packaging. Of these graduates, 113 were Ph.D. degree recipients, 158 were MS recipients, and 120 were BS recipients. The PRC educational program has been acknowledged by its industry partners as one of the best, as it prepares students to "hit the ground running" with a broad set of skills. Students are currently completing degrees at all the three above degree levels with knowledge in RF, Optical and Digital design and fabrication, high density board, area array, wafer level assembly, burn-in, electrical test and reliability. The PRC provides resume posting services for all its students at all degree levels and interested companies can preview resumes at the PRC website. For more information about recruiting, please contact Leyla Conrad (leyla.conrad@ee.gatech.edu).

International Academic Workshop to be Held in Conjunction with ECTC - Sheraton New Orleans Hotel - May 27, 2003
The purpose of the Academic Workshop is to bring together the global academic community, leading eventually to making “packaging” an academic subject. The workshop has been used, since its creation in 1997, by the PRC, to make the academic community aware of the significant advances being made worldwide in the next generation electronic packaging education and to promote international collaborations in areas of mutual interest to serve the global technical community.

From 1998 to 2000, the PRC organized three international workshops at the Georgia Tech campus as an initiative to bring the global academic community together. Two years ago, this workshop was held in Hong Kong and last year, in Dresden, Germany. It is now being integrated into IEEE CPMT Society with its global mission. This year, the Academic workshop will be held in conjunction with ECTC, as a one-day workshop. For further information, please contact Leyla Conrad (leyla.conrad@ece.gatech.edu).

Facilities

PRC Installs New Advanced Plating System
The PRC's 300 mm SOP Wafer Fabrication Laboratory, located in the Manufacturing Research Center at Georgia Tech, has been in operation since March 1997. This class 1000 cleanroom houses a prototype research laboratory that enables the processing of 300 mm SOP substrates by Center personnel. These substrates integrate various enabling technologies by the Center and its industry partners. Existing process capabilities in this laboratory include: large area substrate cleaning and preparation, development and etching, polymer deposition of wet films by either spin or meniscus coating, polymer deposition of dry films, soft bake and final film curing, full field photolithography, plasma etching/cleaning and laser ablation.

The PRC has recently partnered with ATOTECH USA, a plating equipment, chemistry and process provider. The core of this partnership is the development of equipment, chemistries and processes needed to realize ultra-fine board structures needed by the Center for its INC and SOP testbeds and by its member companies.

Towards these goals, the PRC and ATOTECH USA staffs have engineered and manufactured a new vertical electroless and electrolytic plating system. The system is expected to be qualified and operational in the SOP laboratory by the end of this upcoming semester. The system, which is 60’ in length, supports 57 process steps for pre-treatment and plating processes and will be used for panel and pattern plating alike.

The system is extremely flexible in its operational configuration. Process tanks have ultrasonics, heating, cooling, mechanical rack agitation, filtered re-circulation and bubbling. The system can be operated with all, none, or any combination of these features running. Initial capabilities of the system include: electroless copper and nickel, immersion gold, electrolytic copper, tin-lead, with expansion to include silver plating. The system is a modular concept, permitting baths to be swapped out, as chemistry and process needs dictate.

Installation began in December 2002, with the modification of the laboratory infrastructure. With construction of the laboratory nearing completion, the plating system installation will begin mid March 2003 and is anticipated to be operational by July 2003.

It is anticipated that this system will provide the hardware foundation needed to demonstrate the various SOP technologies being developed by the PRC. For further information please contact Dean Sutter (dean.sutter@ee.gatech.edu).

Workshops & Conferences

PRC to Exhibit at 53rd ECTC in New Orleans
The PRC will host an exhibit booth at the 53rd ECTC in New Orleans. Please stop by and say hello and learn the status of the latest packaging technology. The booth (#414) will be in the Sheraton Hotel, 500 Canal Street. For further information, please contact Marcus Johnson (mjohnson@ee.gatech.edu) or visit the PRC website.

PRC, in Partnership with IEEE and Other Organizations, Announces First International Nano Workshop to be Held in Atlanta, March 22-23, 2004
This workshop will take place at the Grand Hyatt Hotel in Atlanta, Georgia. It will focus on Nano and Bio Packaging including Nano Package Design, Bio-Packaging, Sensor Packaging, Packaging Materials & Processes: Dielectrics, Capacitors & Fluidics; Nano Interconnections and Wiring, Thermal Science, Optical Interconnections, and Batteries.

The first workshop will be chaired by Professor Rao R. Tummala of the Georgia Institute of Technology. The International Planning Committee consists of Thom Fischer and Raj Chanchani of Sandia Labs (USA); Douglas Lowndes, ORNL (USA); Lee Loke Chong, Mahadevan Iyer and Andrew Tay (Singapore); Herb Reichl, IZM (Germany); Jim Morris and Ken Gilleo (USA); Johan Liu, Chalmers University (Sweden); Shen-Li Fu (Taiwan); Avi Bar-Cohen, Univ. of Maryland (USA); Srinivas Rao, Solectron (USA); Bruce Kim, Arizona State Univ. (USA), Walt Trybula, Sematech (USA), Ajay Malshe and Bill W. Brown, Univ. of Arkansas (USA).

Anyone interested in participating should send their title and abstract (300 words) electronically to wlp@ee.gatech.edu by October 1, 2003. For further information, please contact Leyla Conrad (leyla.conrad@ece.gatech.edu or visit the PRC website. Download this PDF flyer for the event.

Recent PRC Publications

The following is a short list of recent publications by PRC thrust leaders and their team members. An extensive list can be found on the PRC website. For further information, please contact Angie Hughes (angieh@ee.gatech.edu).

System-On-Package (SOP)
"Digital, RF and Optical Integration in System-on-a-Package (SOP) for Convergent Systems," Tummala, R., Sundaram, V., Liu, F., Dalmia, S., Hobbs, J., Matoglu, E., Davis, M., White, G., Laskar, J., Swaminthan, M., Jokerst, N., Nonaka, T., ICEP 2002, Tokyo, Japan, June 2002.

"Interconnect Opportunities for Gigascale Integration," Meindl, J. D., Davis, J. A., Zarkesh-Ha, P., Patel, C., Martin, K., and Kohl, P. A., IBM Research Journal, 46, 245-265 (2002).

"An Automated Workcell for Meniscus Coating on Large Area Packaging Substrates," Bhattacharya, S., Bhatevara, S., Sutter, D., Kamen, E., May, G., Tummala, R., IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 4, December, 2001, pp 625-630.

Microvia Global Internconnects (MGI)
"The Acceleration of Non-formaldehyde Electroless Copper Plating," Li, J., and Kohl, P.A., Journal of The Electrochemical Society, C631-C636 (2002).

"Fabrication of Microchannels Using Polycarbonates as Sacrificial Materials," Reed, H. A., White, C. E., Rao, V., Allen, S. A., Henderson, C. L., and Kohl, P. A., Journal of Micromechanics and Microengineering, 11, 733-737 (2001).

"Variable Frequency Microwave Curing of Benzocyclobutene," Tanikella, R. V., Allen, S. A., and Kohl, P. A., Journal of Applied Polymer Science, 83, 3055-3067 (2002).

”Reliability Assessment of Microvias in HDI Printed Circuit Boards," Liu, F., Lu, J., Sundaram, V., White, G., Sutter, D., Baldwin, D., Tummala, R., IEEE Transactions on Components and Packaging Technologies, pp 254-259, No. 2, Vol. 25, June 2002.

Reliability
“An Integrated Process Modeling Methodology and Module for Sequential Multilayered Substrate Fabrication using a Coupled Cure-Thermal-Stress Analysis Approach," Dunne, R. C. and Sitaraman, S. K., 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1311-1319. Also, IEEE Transactions - Electronics Packaging Manufacturing, Vol. 25, No. 4, 2002, pp. 326-334.

“Thermo-Mechanical Reliability of Underfilled BGA Packages,” Pyland, J., Pucha, R. V., and Sitaraman, S. K., IEEE Transactions on Components and Packaging Technologies, Vol. 25, No. 2, April 2002, pp. 100-106.

"Thermomechanical Reliability of Microelectronic Packaging," Qu, J., 2003, Interfacial and Nanoscale Failure, ed. W. Gerberich and W. Yang, Elsevier Science.

"Interfacial versus Cohesive Failure on Polymer-Metal Interface- Effects of Interface Roughness," Yao, Q. and Qu, J., 2002, J. Electronic Packaging, Vol. 124, pp.127 - 134.

"Effect of Moisture on the Interfacial Fracture Toughness of Underfill/Solder Mask Interfaces," Ferguson, T. and J. Qu, 2002, J. Electronic Packaging, Vol. 124, pp.106 - 110.

"Effective Elastic Modulus of Underfill Material for Flip-Chip Applications," Qu, J. and Wong, C.P., 2002, IEEE Transactions on Components and Packaging Technology, Vol. 25, pp. 53 - 55.

RF / Integral Passives
"Next Generation Integral Passives: Materials, Processes, and Integration of Resistors and Capacitors on PWB Substrates,” Bhattacharya, S., Tummala, R., Journal of Materials Science, Materials in Electronics, 11 (2000) 253-268.

"Optimization of Nanocomposite Integral Capacitor Fabrication Using Neural Networks and Genetic Algorithms," Thongvigitmanee, T. and May, G., Proc. SEMICON West 2002: SEMI Technology Symposium, San Jose, CA, July, 2002, pp. 123-129.

Optoelectronics
“Integrated Detectors for Embedded Optical Interconnections On Electrical Boards, Modules, and Integrated Circuits,” Cho, S., Seo, S., Brooke, M., Jokerst, N., IEEE Journal of Special Topics in Quantum Electronics: Integrated Optoelectronics, Vol. 8, No. 6, pp. 1427-1434, November/December, 2002.

Assembly
"Electronics Manufacturing: With Lead-Free, Halogen-Free, and Conductive-Adhesive Materials," Lau, J., Wong, C.P., Lee, S.W.R, Lee, N.C., McGraw Hill, New York, NY, (ISBN 0-07-138624-6, 700 pages) 2002.

"Novel No Flow and Reworkable Underfills," Shi, S., Wang, L., Wong, C.P., Encyclopedia of Smart Materials, John Wiley, Vol. 1, p.438-448(2002).

Thermal Management
“Single Chamber Compact Thermosyphons With Micro-fabricated Components,” Murthy, S.S., Joshi, Y., Nakayama, W., IEEE Transactions on Components and Packaging Technologies, Vol. 25, pp. 156-163, 2002.

“A Natural Circulation Model of the Closed Loop, Two-phase Thermosyphon for Electronics Cooling,” Haider, S.I., Joshi, Y.K., Nakayama, W., J. Heat Transfer, Vol. 124, pp. 881-890, 2002.

Contracts & Awards

NIST 2002 ATP Award
Ceramic Matrix Composite Boards for SOP and SIP Electronic Packaging

Project duration: 3 years
Total project (est.): $3,826 K
Requested ATP funds: $1,739 K

PRC and Starfire Systems in Schnectady, NY have been awarded a NIST-ATP grant to develop large area, low-cost and reliable polymer-derived ceramic composite circuit boards capable of supporting microminiaturized electronic systems of the future. This proposed board technology will play a key role in the next generation System-On-Package (SOP) fabrication pioneered by PRC. The board material will have the required mechanical, thermal, and electrical properties — such as high stiffness, low moisture absorption, resistance to warpage, low thermal expansion, and dimensional stability — to support extremely high wiring density, 4-8 layers of fine wiring, and multiple embedded functions.

By designing a board material that matches silicon in expansion, an expensive underfilling process can be avoided. The high stiffness and dimensional stability will give unprecedented advantages in multi-layered fine line wiring with smaller via and capture pads. The PRC will use its electronic systems expertise to develop process and computational models to predict board behavior and properties, layer fine wiring and electronic assemblies on finished boards, and conduct tests to validate that this new technology fulfills the requirements of advanced electronic packaging applications. For further information, please contact Carl Rust (crust@ee.gatech.edu) or Raj Pulugurtha (raj@ee.gatech.edu).

Professional Recognitions & Awards

Suresh K. Sitaraman won the Best Paper Award of IEEE CPMT for "Interfacial Fracture Toughness for Delamination Growth Prediction in a Novel Peripheral Array Package."

Mike Harris was elected to the IEEE Microwave Theory and Techniques Society Administrative Committee (AdCom).

Paul Kohl was named Fellow of The Electrochemical Society.

Rao Tummala was inducted into the Indian National Academy of Engineering.

Jianmin Qu became a Fellow of ASME.

Nan Jokerst received the IEEE Education Society/Hewlett Packard Harriet B. Rigas Medal and became an IEEE Fellow.

Martin Brooke won Georgia Tech’s Outstanding Doctoral Thesis Advisor Award.

Madhavan Swaminathan received Georgia Tech’s Outstanding Graduate Research Advisor Award, Georgia Tech’s Outstanding Faculty Leadership for the Development of Graduate Research Assistants Award, and the Best Student Paper Award at the Topical Meeting on Electrical Performance of Electronic Packaging.

C.P. Wong’s student, Z. Zhang, won 2002 Best MS Thesis Award, Sigma Xi for “No Flow Underfills for Flip Chip Applications,” and also received the Outstanding IEEE ECTC Paper Award for “Double Layer No Flow Underfill Incorporated with Silica."

C.P. Wong was the first recipient of the IEEE CPMT Society's Exceptional Technical Achievement Award for development of silicon gels to achieve reliability without hermeticity in plastic IC packaging.

Manos Tentzeris won the IEEE CPMT Outstanding Young Engineer Award.

David Keezer was recognized for Technical Contributions to the International Test Conference by the IEEE Computer Society.

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