SOP Research at Georgia Tech PRC
The SOP, being pioneered by Georgia Tech PRC, is about ultra miniaturization of systems by thin film component integration. This is what Prof. Rao Tummala calls “ Moore ’s Law for system integration”, akin to Moore ’s Law for ICs. The SOP paradigm changes the current chip-centric SOC methodology to a cheaper, faster-to-market IC-package-system co-design flow. The advantages of the SOP paradigm over SOC appear overwhelming due to SOP’s design simplicity, lower cost and higher system function integration, better electrical performance without the intellectual property issues that dominate SOC. The SOP is also different from and offers advantages over 3D packaging and SIP. The 3D packaging is a general concept of stacking of similar or dissimilar chips such as DRAMs or DRAMs with processor and flash memory. The SIP goes beyond to embed both actives and passives but the passives are currently-available discrete, thick and bulky components. The SOP goes one step further in the ultimate 3D integration of components in thin film form at microscale in the short term, and nanoscale in the long term. The SOP focuses on integrating both single function as well as heterogeneous system functions, optimizing ICs for transistors and packages for integration of digital, RF, optical, sensor and others. It accomplishes this by both build-up thin film SOP, similar to ICs, and stacked SOP, similar to parallel fabrication of organic boards.

The SOP research at PRC includes mixed function systems from design to fabrication to test to reliability. The multifunction substrate starts with a high modulus and low TCE raw substrate on which to build layers of low K and low loss dielectrics and embedded RF components such as capacitors, resistors and inductors, as well as embedded optical waveguides, gratings, lasers and detectors.

The PRC has demonstrated the first SOP package with digital, optical and RF integration last year and is currently working to enhance further component integration, functionality and performance.

Potential applications of SOP are integrated microprocessor packaging for enterprise servers, and digital-RF modules for mobile applications. For further information, contact Chong Yoon (cyoon@ece.gatech.edu)

RESEARCH ADVANCES & INNOVATIONS

A Novel Electromagnetic Bandgap (EBG) Structure for Noise Isolation/Suppression in Mixed-Signal SOP-Based Systems
The PRC team has begun to address one of the most fundamental issues related to mixed signal systems.

Many modern packaging structures support mixed-signal systems where digital and RF/analog circuits exist together. One typical approach to isolate the sensitive RF/analog circuits from the noisy digital circuits is to split the power plane or both power and ground planes. The gap in power plane or ground plane can partially block the propagation of electromagnetic waves. For this reason, split planes are usually used to isolate sensitive RF/analog circuits from noisy digital circuits. Although split planes can block the propagation of electromagnetic waves, part of the electromagnetic energy can still couple through the gap. Hence, this method only provides a marginal isolation (-20 dB ~ -60 dB) at high frequencies (usually above ~ 1 GHz) and could create a serious problem as the sensitivity of RF circuits increases and operating frequency of the system increases. Generally, split planes provide a good isolation (-70 dB ~ -80 dB) at low frequencies (usually below ~ 1 GHz) but show a poor isolation (-20 dB ~ -60 dB) at high frequencies due to electromagnetic coupling. In addition to this, split planes sometimes require separate power supplies to maintain the same DC level, which is not cost-effective. The use of ferrite beads have been suggested as a solution to these problems, enabling increased isolation as well as the use of a single power supply; however, due to the high sensitivity of the RF circuitry, the amount of isolation provided by ferrite beads again tends to be insufficient at high frequencies. Therefore, the development of better noise isolation method is critical for good performance of mixed-signal system. A novel electromagnetic bandgap (EBG) structure called the alternating impedance EBG (AI-EBG) was developed by Prof Swaminathan’s team at Georgia Tech . This novel EBG structure shows excellent isolation (-100 dB ~ -120 dB), which provides a noise-coupling free environment in mixed-signal systems. A U.S. patent has been filed on this invention recently. For further information, please contact Jinwoo Choi, Vinu Govind or Madhavan Swaminathan, School of Electrical and Computer Engineering, Georgia Institute of Technology

PRC Showcases Its Leading-edge Baseline Process during NSF Site Visit

10um (left) and 6um lines (right) and spaces demonstrated in SOP4 baseline process test vehicle using semi-additive plating process on BCB dielectric

The Packaging Research Center is developing its next generation baseline process technology for multi-functional, microminiaturized System-on-a-Package (SOP) modules, both for mobile and desk top applications. The baseline process has six leading–edge technologies, including: 1) low CTE, high modulus C-SiC composite substrates for Cu-low K reliability, 2) high density build-up wiring with low loss dielectrics, 3) embedded thin film passive components (C, R, L), 4) embedded RF components, 5) embedded optical interconnects with polymer waveguides, and 6) 100µm pitch lead-free solder flip-chip and wafer level packaging ( WLP ). The current process is based on low CTE (2.5-3ppm/C), high modulus (200-300GPa) C-SiC composite substrates as well as on high performance organic laminates like Asahi A-PPE and MCL-E-679F (Hitachi Chemical). The build-up dielectric used is 10µm thick BCB (Dow Chemical) which has a low Dk (2.65) and low loss tangent (0.0008) at GHz frequencies. The ultra high density wiring consists of up to five build-up metal layers with 10-12µm lines and spaces and 5µm copper thickness. Stacked microvias down to 20µm diameter, fabricated using excimer laser ablation are used to interconnect layers. The SOP substrate team has recently integrated embedded capacitors with 0.5-1µF/cm2 capacitance density using hydrothermal synthesized BaTiO3 thin films (<1µm thickness). Embedded thin film resistors have been integrated by laminating metal foils (Gould Electronics). Embedded optical interconnects have been fabricated using BCB and siloxane waveguides and embedded lasers and photodetectors. Low cost electroless and electrolytic plating processes have been demonstrated on BCB using plasma surface treatment and 6-8µm line widths and spaces have been achieved.

The SOP4 baseline process was implemented in a series of process test vehicles and initial results on signal transmission with the above embedded components were showcased at the NSF and IAB meetings in September 2004. The latest baseline process is now being used to develop RF-Digital and Digital-Optical functional modules and these demonstrations are anticipated in Fall 2005.

The PRC baseline team consists of PRC research scientists and engineers, visiting industry engineers, faculty and students and the baseline process involves research from design, fabrication, test and reliability of both PRC and industry SOP prototypes. For further information on the PRC baseline process and functional SOP prototypes, please contact Venky Sundaram (vsunda@ece.gatech.edu) or Prof. Rao Tummala (rtummala@ece.gatech.edu)

IEEE Special Issue on SOP Technology
Georgia Tech Packaging Research Center has been the pioneer in developing the SOP (System-on-Package) concept. A team of faculty, engineers, scientists, and students have been working both in fundamental and system level aspects of the SOP since Prof. Rao Tummala first introduced the concept in 1994. Prof. Tummala views SOP as Moore ’s law for systems, akin to Moore ’s Law for ICs, except SOP integrates system components by thin film technologies at microscale in the short term and nanoscale in the long run for digital convergence of mixed-signal electronic and bio-electronic systems. Unlike SIP, MCM or SOC, SOP is a system technology with all the system functions and interconnections and takes advantage of the synergy between IC, package and the system.

Recently, for the first time, the IEEE Transactions on Advanced Packaging published a Special Issue on SOP in May, 2004. This dedicated issue consists of 19 contributed papers by leading experts around the globe. This issue begins with an introduction of SOP, written by the editor of the special issue, Prof. Rao Tummala which is followed by three general SOP concept papers. The next three papers deal with signal integrity, power integrity, and EMI. The following seven papers deal with fabrication and integration issues including optoelectronics, digital, and RF integration. The next series of five papers are on thermal, assembly, reliability, electrical test, and manufacturing. This special issue covers almost all aspects of SOP for highly miniaturized systems by means of IC-Package-System integration.

IEEE members may read this special issue by logging on at www.cpmt.org/trans

PUBLICATIONS

PRC Publications on SOP (2004 only)

Search ALL PRC Publications (1993-2004)

1. Pucha, R.V., Sitaraman, S.K., Hegde, S., Damani, M., Wong, C.P., Qu, J., Zhang, Z., Raj, P.M., Tummala, R.R., "Materials and mechanics
   challenges in SOP-based convergent Microsystems," In Micromaterials and Nanomaterials, A publication series of the Micro Materials Center Berlin at the Fraunhofer Institute IZM, Issue No. 3, 2004, pp.16-29.
2. Pucha, R.V., Hegde, S., Damani, M., Tunga, K., Perkins, A., Mahalingam, S., Ramakrishna, G., Lo, G., Klein, K., Ahmad, J., and Sitaraman, S.K. "System-level reliability assessment of mixed-signal convergent microsystems," IEEE Transactions on Advanced Packaging, June 2004, (In Press).
3. Mahalingam, S., Hegde, S., Ahmad, J., Pucha R.V., Sundaram, V., Liu, F., Tummala, R., and Sitaraman, S.K., "Materials, process and reliability of mixed-signal substrates for SOP technology," Proceedings of the 54th Electronic Components and Technology Conference, 2004, pp. 1630-1635.
4. Sundaram, V., Tummala, R., White, G., Lim, K., Wan, L., Guidotti, D., Liu, F., Bhattacharya, S., Raj, P.M., Abothu, I.R., Doraiswami, R., Pucha, R.V., Laskar, J., Tentzeris,M., Chang, G.K., Swaminathan, M., "System-on-a-Package (SOP) substrate and module with Digital, RF, and Optical integration," Proceedings of the 54th Electronic Components and Technology Conference, 2004, pp. 17-23.
5. Sundaram, V., Tummala, R., White, G., Lim, K., Wan, L., Guidotti, D., Liu, F., Bhattacharya, S., Raj, P.M., Abothu, I.R., Doraiswami, R.,  Pucha, R.V., Sitaraman, S., Laskar, J., Tentzeris,M., Chang, G.K., Swaminathan, M., 2004, "First single module demonstration of SOP with Digital, Optical and RF for last mile broadband applications," Proceedings of the International Conference on Electronics Packaging, Japan, 2004, pp. 399-404.
6. S. Pinel , CH. Lee, S. Nuttinck, S-W. Yoon, K.Lim, and J. Laskar, “Embedded IC and high Q passives technology for ultra-compact Ku-Band VCO module” , IEEE-Microwave and Wireless Components Letter, VOL. 14, NO.12, February 2004, pp 80-82.
7. M. Tentzeris, J. Laskar, J. Papapolymerou, S. Pinel , V. Palazzari, R.Li, G. DeJean, N. Papageorgiou, D. Thompson, R. Bairavasubramanian, S. Sarkar, J-H Lee. “3D Integrated RF and Millimeter-waves Functions and Module using System-On-Package Technology”, IEEE special issue on SOP, 2004.
8. Rana Pratap, Daniela Staciulescu Stephane Pinel, Joy Laskar, Gary May, “Modeling and Sensitivity Analysis of Circuit Parameters for Flip Chip Interconnects Using Neural Networks”, Accepted at Transactions on Advanced Packaging.
9. S. Pinel, R.Pratap, N.Papageorgiou, S.Sarkar and J. Laskar, “Tri-dimensional micro-channel technology for System-On-Package nano-fluidic nano-system, nano-sensor and Lab-On-Chip” Nano-Bio Packaging conference 2004.
10. J. Laskar, S. Nuttinck , and S. Pinel, “Thermal Management of High Power Devices”, GAAS ManTech 2004, INVITED Paper
11. R.Pratap, S.Sarkar, S.Pinel, J.Laskar, G.May. “Modeling and Optimization of Multilayer LTCC Inductors for RF/Wireless Applications Using Neural Networks and Genetic Algorithms” 54th ECTC 2004
12. Valeria Palazzari, Dane Thompson, S.Pinel, Jong Hoon Lee, Saikat Sarkar, Rana Pratap, Nikko Papageorgiou, Gerald DeJean, Ramanan Bairavasubramanian Rong-Lin Li, Manos Tentzeris, Joy Laskar, John Papapolymerou, and Luca Roselli, “Multi-band RF and mm-Wave Design Solutions for Integrated RF Functions in Liquid Crystal Polymer System-On-Package Technology” 54th ECTC 2004
13. Kyutae Lim, Lixi Wan, Daniel Guidotti, S.Pinel, Venky Sundaram, George White, Fuhan Liu, Swapan Bhattacharya, Ravi Doraiswami, Yin-Jung Chang Saikat Sarkar, Rana Pratap, Sang-Woong Yoon, Moonkyun Maeng, Joy Laskar, Manos Tentzeris, G. K. Chang, Madhavan Swaminathan and Rao Tummal, “System-on-a-Package (SOP) Module Development for a Digital, RF and Optical Mixed Signal Integrated System”, 54th ECTC 2004
14. S.Sarkar, V.Palazarri, G.Wang, N. Papageorgiou, D. Thompson, J.H.Lee, S.Pinel, M.M.Tentzeris, J.Papapolymerou, J.Laskar, “RF and mm-Wave SOP Module Platform using LCP and RF MEMS Technologies” MTT 2004
15. Rana J. Pratap, Saikat Sarkar, S.Pinel, Joy Laskar, and Gary S. May, “ Modeling and Optimization of Multilayer RF Passives Using Coupled Neural Networks and Genetic Algorithms”, MTT 2004
16. S.Sarkar, N.Papageorgiou, R. J. Pratap, S.Pinel, J. Laskar, and G. S. May, “ Novel modelling and layout optimization technique for Highly compact planar bandpass filters”, EuroMW 2004
17. J.-H.Lee, G.DeJean, S. Sarkar, S. Pinel, K. Lim, J.Papapolymerou, M. Tentzeris and J. Laskar, “ Advanced 3-D LTCC System-on-Package (SOP) architectures”, for Highly Integrated Millimeter-Wave Wireless Systems , EuroMW 2004
18. Rana J. Pratap, Saikat Sarkar, Stephane Pinel, Joy Laskar, and Gary S. May, “ Modeling and Design of Compact Multilayer LCP Filters for 802.11 WLAN Applications Using Coupled Neural Networks and Genetic Algorithms”, IMAPS 2004
19. Rana J. Pratap,, Stephane Pinel, Joy Laskar, and Gary S. May, “ Millimeter Wave Filter Synthesis Using Neuro-Genetic Algorithms”, Submitted to APMC 2004
20. S. Pinel, S. Sarkar , R.Bairavasubramanian, J. H. Lee, M. Tentzeris, J.Papapolymerou and J. Laskar, “Highly Integrated LTCC and LCP Millimeter Wave Functions For 3D-SOP High Data Rate Wireless Systems." Submitted to APMC 2004
21. R.L.Li, G.DeJean, J.Laskar and M.M.Tentzeris, “Development and Analysis of a Folded Shorted-Patch Antenna with Reduced Size", IEE E Transactions on Antennas and Propagation in April 2004.
22. M.M.Tentzeris and N.Bushyager, “Electromagnetics: Time-Domain Techniques", Invited Chapter for the book: The RF/Microwave Applications: Challenges and Solutions, edited by K.Cheng, to be published by Wiley Eds., January 2004.
23. K.Lim, S.Pinel, J.Laskar and M.M.Tentzeris, “RF/Wireless Packaging", Invited Chapter for the book: The RF/Microwave Applications: Challenges and Solutions, edited by K.Cheng, to be published by Wiley Eds., January 2004.
24. Fuhan Liu, Rao R Tummala, Venky Sundaram, Daniel Guidotti, Zhorn Huang, Y-J Chang, Isaac Robin Abothu, P M Raj, Swapan Bhattacharya, Devarajan Balaraman, G K Chang, "Multifunctional Integrated Substrate Technology for High Density SOP Packaging", accepted for presentation at 6th IEEE CPMT conference on High Density Microsystem Design and Packaging, Shanghai, China, June 30-July 3, 2004.
25. Isaac Robin Abothu, P. Markondeya Raj, Devarajan Balaraman, Swapan Bhattacharya, Michael D. Sacks and Rao Tummala, "Development of high K embedded Capacitors on printed wiring board using sol-gel and foil transfer processes", Presented at The 54th Electronic Components and Technology Conference, ECTC 2004 held at Las Vegas, Nevada during June 1-4, 2004 (Proceedings page 514-520, 2004).
26. Devarajan Balaraman, Jinwoo Choi, Vijay Patel, P. Markondeya Raj, Isaac Robin Abothu, Swapan Bhattacharya, Lixi Wan, Madhavan Swaninathan and Rao Tummala, "Simultaneous Switching Noise Suppression Using Hydrothermal Barium Titanate Thin Film Capacitors", Presented at The 54th Electronic Components andTechnology Conference, ECTC 2004 held at Las Vegas, Nevada during June 1-4, 2004 (Proceedings page 514-520, 2004) (Proceedings Pages: 282-288, 2004).
27. Venky Sundaram, Rao Tummala, George White, Kyutae Lim, Lixi Wan, Daniel Guidotti, Fuhan Liu, Swapan Bhattacharya, Raj M. Pulugurtha, Isaac Robin Abothu, Ravi Doraiswami, Raghuram V. Pucha, Joy Laskar, Manos Tentzeris, G.K. Chang and Madhavan Swaminathan, "System-On-a Package (SOP) Substrate and Module with Digital, RF and Optical Integration",  Presented at The 54th Electronic Components and Technology Conference, ECTC 2004 held at Las Vegas, Nevada during June 1-4, 2004 (Proceedings Pages: 17-23, 2004).
28. Ankur Aggarwal, Pulugurtha Raj, Isaac Robin Abothu, Michael Sacks, Rao Tummala and Andrew Tay, "New paradigm in IC-Package interconnections by Reworkable Nano-Interconnects", Presented at The 54th Electronic Components and Technology Conference, ECTC 2004  held at Las Vegas, Nevada during June1-4, 2004 (Proceedings Pages: 451-460, 2004). Received Best Student Paper Award from INTEL Corporation.
29. Venky Sundaram, Rao Tummala, George White, Kyutae Lim, Lixi Wan, Daniel Guidotti, Fuhan Liu, Swapan Bhattacharya, Raj M. Pulugurtha, Isaac Robin Abothu, Ravi Doraiswami, Raghuram V. Pucha,  Suresh Sitaraman, Joy Laskar, Manos Tentzeris, , G.K. Chang and Madhavan Swaminathan, "First Single Module Demonstration of SOP with Digital, Optical and RF for Last Mile Broadband Applications", Presented at International Conference on Electronics Packaging held at Tokyo, Japan during April 14-16, (Proceedings: pp. 399-404, 2004).

AWARDS & RECOGNITION

Outstanding Student Award
Ankur Aggarwal, a graduate student of PRC has received Intel Corporation Best Student Paper Award for his presentation entitled "New Paradigm in IC Package Interconnections by Reworkable Nano-interconnects" at The 54th Electronic Components and Technology Conference, ECTC 2004  held at Las Vegas, Nevada during June 1-4, 2004 (Proceedings Pages: 451-460, 2004).

Special Honor
Professor Rao R. Tummala, director of the Packaging Research Center , received a special plaque as an expression of honor and appreciation by the PRC’s faculty, administrative and research staff for his ten years of vision, leadership, dedication and research innovations. The award was presented on September 23, 2004 by Professor C. P. Wong and Paul Kohl, PRC faculty members, during the PRC’s 10 th anniversary celebration held at the Georgia Tech Hotel and Convention Center.

INTERNATIONAL COLLABORATIONS

German Interns at the PRC 2004-2005
PRC welcomes TUD students Karsten Meier and Björn Böhme

German interns Karsten Meier and Björn Böhme seated at a Dektak 3030 profilometer

We are two German students from the Dresden University of Technology (TUD – Dresden, Germany ). Currently we are in the ninth semester and as a part of the German Diploma schedule we have to pass an internship. The minimum duration of this has to be eighteen weeks.

Concerning the expanding relationship between the Packaging Research Center and the Dresden University of Technology, we decided to use this opportunity of interning at such a well known center as the PRC.

We will work in the “Next Generation Substrate Laboratory” for a period of six months (Sept. 2004 to Feb. 2005). Furthermore, we will be gaining experience with the people and the country.

Our last projects at the TUD dealt with reliability issues of package-board-interconnections, especially, the influence of thermal stress which was the focus of our investigations. Therefore we used standardized High Temperature Storage, Temperature Cycle Tests and Shearing Tests.

Presently we are working under the guidance of Venky Sundaram on research tasks depending on the PRCs SOP visions. We are involved in manufacturing next generation high density and multilayer printed wiring boards (PWB). This involves operating equipment and processes like spin coater, plasma tool, lamination tool as well as the wet chemical processes. To employ new materials it is necessary to analyze and optimize every individual process step. Therefore several methods are used, for example, a profilometer, a video microscope including computerized measurement or preparing cross-sections are utilized to gain data for the different process steps.

Working in the substrate lab gives us the opportunity to get advanced experience in next generation technologies of electronics packaging as well as cultural and linguistic experiences. So we also spend some leisure time with the colleagues.

In March 2005, we will leave Atlanta to return to Dresden where we will be continue working on our diploma thesis for one more semester to achieve the Diploma degree from the TUD.

EDUCATION

PRC High School Student Intern Wins First Place in NAACP Competition

Ms. Payne and her two award winning students with their mentors, Prof. Joshi and graduate student, Camil Ghiu

EVENTS

PRC Celebrates a Decade of Innovations
On September 23, 2004 , Georgia Tech PRC celebrated its tenth year as NSF Engineering Research Center . The event, held at the Georgia Tech Hotel and Conference Center , featured keynote presentations from industry visionaries, academia, and government. Following Jean-Lou Chameau’s (provost of Georgia Tech) and Lynn Preston’s (head of NSF ERC) welcome and their investments in PRC, professor Tummala presented the PRC's new vision for new industry and how its cornerstone concept, "System-on-Package" (SOP), is becoming the new technology platform for digital convergence of computer, communication, consumer and biomedical systems. He described SOP as the 2 nd Moore ’s Law — this time, for system integration, and as the future driving engine for mega-function electronics. He also conveyed the message that SOP and SIP are not identical; the former being system-centric, opposed to the latter, being IC-centric. Georgia Tech’s vice-provost, Charlie Liotta, and dean of engineering, Don Giddens, shared their views of the PRC as the model for other Centers at Georgia Tech.

The next session dealt with local, national and international impacts of the PRC since its inception in 1994. The local impact was addressed by Michael Cassidy, president of the Georgia Research Alliance and J. David Roessner, associate director at SRI International; they concluded that the PRC has been the best model so far with the State of Georgia receiving the equivalent of $9 of benefit for every $1 invested. The U.S. impact of the PRC was presented by IAB officer Len Chorinsinski of Northrop Grumman, Jay McNamara, CEO of Endicott Interconnect Technologies; Herb Reichl, professor and director of Fraunhofer Institute for Reliability and Microintegration; and Chang Chieh Hang, recent deputy chairman of A*Star-Singapore.

Professor Gary May, Georgia Tech, headed up a session on the educational impacts of the PRC and invited Gil Vandentop, manager at Intel, to talk about the quality of PRC engineers hired by Intel. A panel of former PRC students now employed by industry and academia included Nicole Grove, packaging engineer at Freescale; Eric Fitzgerald, engineer at Schlumberger; Hitesh Windlass, Intel; and Jose Cruz-Rivera, University of Puerto Rico-Mayaguez. Each shared testimonials as to the value of the PRC packaging education programs in their successful careers. A combined lunch and poster session led by PRC associate director, Leyla Conrad, provided an opportunity for current PRC students to present their research projects to the 10th anniversary participants.

The most important session involved industry visionaries from computing, communication, semiconductor, consumer and networking giants. Vijay Lund, VP of IBM; Tom MacTavish, VP of Motorola; Stan Lumish, CTO of JDS Uniphase; Nasser Grayeli, VP of Intel; and Choon-Ho Kim, president of KETI-Korea, were the featured keynote speakers. Each reviewed there view of technology for the next decade. Following these visionary talks, the PRC's five research alliance leaders professors Madhavan Swaminathan, Joy Laskar, Gee-Kung Chang, C. P. Wong, and Rao Tummala, reviewed a look back of their team’s innovations in each of their respective research areas.

After a social hour and dinner, Jean-Lou Chameau, master of ceremonies, tipped off the evening introducing celebratory talks by Georgia Tech president, Wayne Clough, who spoke of the PRC's decade of accomplishments; Bill Todd, president and CEO of the Georgia Cancer Coalition, who gave a historical perspective of the PRC; and John Brighton, director of engineering for the NSF, who gave his perspective on the NSF’s ERC program and the PRC's contributions to it. Michael Cassidy spoke again and presented the economic impact of the PRC, as did Nasser Grayeli, who shared the packaging industry's perspective of the PRC’s contributions to new packaging technologies.

A day of talks and festivities ended with special recognition and a plaque presented to Professor Tummala by Georgia Tech PRC faculty, research and administrative staff, for a decade of leadership and achievements. This presentation was followed by his expressions of gratitude to numerous people and organizations who supported the PRC and contributed to its success over the past decade. Several gifts and recognitions were presented by Professor Tummala to recipients throughout the day as appreciation for their exceptional support and dedication.

Nano & Bio-Electronic Packaging Workshop
March 22-23, 2005 , Atlanta , Georgia

The second International Workshop on Nano & Bio-Electronic Packaging will be held at the Georgia Tech Technology Square Research Building, March 22 and 23, 2005.

Titles and abstracts are due November 12, 2004 . Those interested in submitting an abstract and/or attending the workshop , please visit and register online at www.prc.gatech.edu/nanobiopack

First International Workshop on 3S (SOP, SIC, SOC) Electronic Technologies
September 22 & 23, 2005
Global Learning & Conference Center at Technology Square
84 Fifth Street , Atlanta , GA , 30308 USA

The SOP paradigm changes the current chip-centric SOC methodology to a cheaper, faster-to-market IC-package-system co-design flow. The advantages of the SOP paradigm over SOC appear overwhelming due to SOP’s design simplicity, lower cost and higher system function integration, electrical performance, without the intellectual property issues that dominate SOC. SOP is also different from, and offers advantages over, 3D packaging and SIP. The 3D packaging is typically stacking of similar, or dissimilar, chips such as DRAM S. SIP goes beyond to embed both actives and passives but the passives are discrete, thick and bulky components. SOP goes one step further in the ultimate 3D integration of components in thin film form at microscale, in the short term, and nanoscale in the long term. SOP focuses on integrating both single function as well as heterogeneous system functions, optimizing ICs for transistors and package for integration of digital, RF, optical, sensor and others. It accomplishes this by both build-up SOP—similar to ICs—and stacked SOP, which is similar to parallel board fabrication.

This workshop reviews the latest R & D and manufacturing status of each of the three electronic technologies around the world. It will also attempt to compare and contrast SOC, 3D stacking, SIP, SOP and MCM.

For registration and continuously updated info, visit: www.prc.gatech.edu/3s

INFRASTRUCTURE & ENGINEERING SERVICES

Wafer Level 100 Micron Pitch Flip Chip with Lead-free Bumping
The PRC is currently working with a select number of industry partners toward the development of lead-free solder bumping targeted at 100 micron pitch flip chip applications. Progress in this effort includes project partnerships with various members as well as the development, fabrication and installation of a test-bed electro-plating system capable of plating 4-8" wafers in the newly constructed cleanroom laboratory at PRC headquarters in the Manufacturing Research Center at Georgia Tech.

PRC Installs ESPEC Thermal Cycling Chamber
Recent SOP Module Laboratory enhancements include the upgrading of the Reliability Lab to include a new ESPEC Model ET15, AGREE Chamber. The 30w X 30h X 30d chamber size provides the capability to process 425 L (15 cu. ft.) of material. Performance characteristics include temperature ranges from -73 °C to 177 °C, with a temperature ramp of 5 °C/min or greater, and the ability to incorporate mechanical or electro-dynamic vibration tables into the test chamber.

The Center is currently in need of a vibration table set-up to fit the system. This need represents an opportunity for in-kind contribution for membership to the PRC.