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Month’s Research Focus: System-On-Package
(SOP) Research
SOP
Research at Georgia Tech PRC The SOP research at PRC includes mixed function systems from design to fabrication to test to reliability. The multifunction substrate starts with a high modulus and low TCE raw substrate on which to build layers of low K and low loss dielectrics and embedded RF components such as capacitors, resistors and inductors, as well as embedded optical waveguides, gratings, lasers and detectors. The PRC has demonstrated the first SOP package with digital, optical and RF integration last year and is currently working to enhance further component integration, functionality and performance. Potential applications of SOP are integrated microprocessor packaging for enterprise servers, and digital-RF modules for mobile applications. For further information, contact Chong Yoon (cyoon@ece.gatech.edu)
RESEARCH ADVANCES & INNOVATIONS A
Novel Electromagnetic Bandgap (EBG) Structure for Noise Isolation/Suppression
in Mixed-Signal SOP-Based Systems Many modern packaging structures support mixed-signal systems where digital and RF/analog circuits exist together. One typical approach to isolate the sensitive RF/analog circuits from the noisy digital circuits is to split the power plane or both power and ground planes. The gap in power plane or ground plane can partially block the propagation of electromagnetic waves. For this reason, split planes are usually used to isolate sensitive RF/analog circuits from noisy digital circuits. Although split planes can block the propagation of electromagnetic waves, part of the electromagnetic energy can still couple through the gap. Hence, this method only provides a marginal isolation (-20 dB ~ -60 dB) at high frequencies (usually above ~ 1 GHz) and could create a serious problem as the sensitivity of RF circuits increases and operating frequency of the system increases. Generally, split planes provide a good isolation (-70 dB ~ -80 dB) at low frequencies (usually below ~ 1 GHz) but show a poor isolation (-20 dB ~ -60 dB) at high frequencies due to electromagnetic coupling. In addition to this, split planes sometimes require separate power supplies to maintain the same DC level, which is not cost-effective. The use of ferrite beads have been suggested as a solution to these problems, enabling increased isolation as well as the use of a single power supply; however, due to the high sensitivity of the RF circuitry, the amount of isolation provided by ferrite beads again tends to be insufficient at high frequencies. Therefore, the development of better noise isolation method is critical for good performance of mixed-signal system. A novel electromagnetic bandgap (EBG) structure called the alternating impedance EBG (AI-EBG) was developed by Prof Swaminathan’s team at Georgia Tech . This novel EBG structure shows excellent isolation (-100 dB ~ -120 dB), which provides a noise-coupling free environment in mixed-signal systems. A U.S. patent has been filed on this invention recently. For further information, please contact Jinwoo Choi, Vinu Govind or Madhavan Swaminathan, School of Electrical and Computer Engineering, Georgia Institute of Technology |
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PRC Showcases Its Leading-edge Baseline Process during NSF Site Visit
The Packaging Research Center is developing its next generation baseline process technology for multi-functional, microminiaturized System-on-a-Package (SOP) modules, both for mobile and desk top applications. The baseline process has six leading–edge technologies, including: 1) low CTE, high modulus C-SiC composite substrates for Cu-low K reliability, 2) high density build-up wiring with low loss dielectrics, 3) embedded thin film passive components (C, R, L), 4) embedded RF components, 5) embedded optical interconnects with polymer waveguides, and 6) 100µm pitch lead-free solder flip-chip and wafer level packaging ( WLP ). The current process is based on low CTE (2.5-3ppm/C), high modulus (200-300GPa) C-SiC composite substrates as well as on high performance organic laminates like Asahi A-PPE and MCL-E-679F (Hitachi Chemical). The build-up dielectric used is 10µm thick BCB (Dow Chemical) which has a low Dk (2.65) and low loss tangent (0.0008) at GHz frequencies. The ultra high density wiring consists of up to five build-up metal layers with 10-12µm lines and spaces and 5µm copper thickness. Stacked microvias down to 20µm diameter, fabricated using excimer laser ablation are used to interconnect layers. The SOP substrate team has recently integrated embedded capacitors with 0.5-1µF/cm2 capacitance density using hydrothermal synthesized BaTiO3 thin films (<1µm thickness). Embedded thin film resistors have been integrated by laminating metal foils (Gould Electronics). Embedded optical interconnects have been fabricated using BCB and siloxane waveguides and embedded lasers and photodetectors. Low cost electroless and electrolytic plating processes have been demonstrated on BCB using plasma surface treatment and 6-8µm line widths and spaces have been achieved. The SOP4 baseline process was implemented in a series of process test vehicles and initial results on signal transmission with the above embedded components were showcased at the NSF and IAB meetings in September 2004. The latest baseline process is now being used to develop RF-Digital and Digital-Optical functional modules and these demonstrations are anticipated in Fall 2005. The PRC baseline team consists of PRC research scientists and engineers, visiting industry engineers, faculty and students and the baseline process involves research from design, fabrication, test and reliability of both PRC and industry SOP prototypes. For further information on the PRC baseline process and functional SOP prototypes, please contact Venky Sundaram (vsunda@ece.gatech.edu) or Prof. Rao Tummala (rtummala@ece.gatech.edu) |
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IEEE
Special Issue on SOP Technology Recently, for the first time, the IEEE Transactions on Advanced Packaging published a Special Issue on SOP in May, 2004. This dedicated issue consists of 19 contributed papers by leading experts around the globe. This issue begins with an introduction of SOP, written by the editor of the special issue, Prof. Rao Tummala which is followed by three general SOP concept papers. The next three papers deal with signal integrity, power integrity, and EMI. The following seven papers deal with fabrication and integration issues including optoelectronics, digital, and RF integration. The next series of five papers are on thermal, assembly, reliability, electrical test, and manufacturing. This special issue covers almost all aspects of SOP for highly miniaturized systems by means of IC-Package-System integration. IEEE members may read this special issue by logging on at www.cpmt.org/trans |
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PUBLICATIONS PRC Publications on SOP (2004 only) Search ALL PRC Publications (1993-2004)
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AWARDS & RECOGNITION Outstanding
Student Award Special
Honor |
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INTERNATIONAL COLLABORATIONS German
Interns at the PRC 2004-2005
We are two German students from the Dresden University of Technology (TUD – Dresden, Germany ). Currently we are in the ninth semester and as a part of the German Diploma schedule we have to pass an internship. The minimum duration of this has to be eighteen weeks. Concerning the expanding relationship between the Packaging Research Center and the Dresden University of Technology, we decided to use this opportunity of interning at such a well known center as the PRC. We will work in the “Next Generation Substrate Laboratory” for a period of six months (Sept. 2004 to Feb. 2005). Furthermore, we will be gaining experience with the people and the country. Our last projects at the TUD dealt with reliability issues of package-board-interconnections, especially, the influence of thermal stress which was the focus of our investigations. Therefore we used standardized High Temperature Storage, Temperature Cycle Tests and Shearing Tests. Presently we are working under the guidance of Venky Sundaram on research tasks depending on the PRCs SOP visions. We are involved in manufacturing next generation high density and multilayer printed wiring boards (PWB). This involves operating equipment and processes like spin coater, plasma tool, lamination tool as well as the wet chemical processes. To employ new materials it is necessary to analyze and optimize every individual process step. Therefore several methods are used, for example, a profilometer, a video microscope including computerized measurement or preparing cross-sections are utilized to gain data for the different process steps. Working in the substrate lab gives us the opportunity to get advanced experience in next generation technologies of electronics packaging as well as cultural and linguistic experiences. So we also spend some leisure time with the colleagues. In March 2005, we will leave Atlanta to return to Dresden where we will be continue working on our diploma thesis for one more semester to achieve the Diploma degree from the TUD. |
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EDUCATION PRC
High School Student Intern Wins First Place in NAACP Competition
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EVENTS PRC
Celebrates a Decade of Innovations The next session dealt with local, national and international impacts of the PRC since its inception in 1994. The local impact was addressed by Michael Cassidy, president of the Georgia Research Alliance and J. David Roessner, associate director at SRI International; they concluded that the PRC has been the best model so far with the State of Georgia receiving the equivalent of $9 of benefit for every $1 invested. The U.S. impact of the PRC was presented by IAB officer Len Chorinsinski of Northrop Grumman, Jay McNamara, CEO of Endicott Interconnect Technologies; Herb Reichl, professor and director of Fraunhofer Institute for Reliability and Microintegration; and Chang Chieh Hang, recent deputy chairman of A*Star-Singapore. Professor Gary May, Georgia Tech, headed up a session on the educational impacts of the PRC and invited Gil Vandentop, manager at Intel, to talk about the quality of PRC engineers hired by Intel. A panel of former PRC students now employed by industry and academia included Nicole Grove, packaging engineer at Freescale; Eric Fitzgerald, engineer at Schlumberger; Hitesh Windlass, Intel; and Jose Cruz-Rivera, University of Puerto Rico-Mayaguez. Each shared testimonials as to the value of the PRC packaging education programs in their successful careers. A combined lunch and poster session led by PRC associate director, Leyla Conrad, provided an opportunity for current PRC students to present their research projects to the 10th anniversary participants. The most important session involved industry visionaries from computing, communication, semiconductor, consumer and networking giants. Vijay Lund, VP of IBM; Tom MacTavish, VP of Motorola; Stan Lumish, CTO of JDS Uniphase; Nasser Grayeli, VP of Intel; and Choon-Ho Kim, president of KETI-Korea, were the featured keynote speakers. Each reviewed there view of technology for the next decade. Following these visionary talks, the PRC's five research alliance leaders professors Madhavan Swaminathan, Joy Laskar, Gee-Kung Chang, C. P. Wong, and Rao Tummala, reviewed a look back of their team’s innovations in each of their respective research areas. After a social hour and dinner, Jean-Lou Chameau, master of ceremonies, tipped off the evening introducing celebratory talks by Georgia Tech president, Wayne Clough, who spoke of the PRC's decade of accomplishments; Bill Todd, president and CEO of the Georgia Cancer Coalition, who gave a historical perspective of the PRC; and John Brighton, director of engineering for the NSF, who gave his perspective on the NSF’s ERC program and the PRC's contributions to it. Michael Cassidy spoke again and presented the economic impact of the PRC, as did Nasser Grayeli, who shared the packaging industry's perspective of the PRC’s contributions to new packaging technologies. A day of talks and festivities ended with special recognition and a plaque presented to Professor Tummala by Georgia Tech PRC faculty, research and administrative staff, for a decade of leadership and achievements. This presentation was followed by his expressions of gratitude to numerous people and organizations who supported the PRC and contributed to its success over the past decade. Several gifts and recognitions were presented by Professor Tummala to recipients throughout the day as appreciation for their exceptional support and dedication. |
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Nano & Bio-Electronic
Packaging Workshop The second International Workshop on Nano & Bio-Electronic Packaging will be held at the Georgia Tech Technology Square Research Building, March 22 and 23, 2005. Titles and abstracts are due November 12, 2004 . Those interested in submitting an abstract and/or attending the workshop , please visit and register online at www.prc.gatech.edu/nanobiopack |
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First
International Workshop on 3S (SOP, SIC, SOC) Electronic Technologies The SOP paradigm changes the current chip-centric SOC methodology to a cheaper, faster-to-market IC-package-system co-design flow. The advantages of the SOP paradigm over SOC appear overwhelming due to SOP’s design simplicity, lower cost and higher system function integration, electrical performance, without the intellectual property issues that dominate SOC. SOP is also different from, and offers advantages over, 3D packaging and SIP. The 3D packaging is typically stacking of similar, or dissimilar, chips such as DRAM S. SIP goes beyond to embed both actives and passives but the passives are discrete, thick and bulky components. SOP goes one step further in the ultimate 3D integration of components in thin film form at microscale, in the short term, and nanoscale in the long term. SOP focuses on integrating both single function as well as heterogeneous system functions, optimizing ICs for transistors and package for integration of digital, RF, optical, sensor and others. It accomplishes this by both build-up SOP—similar to ICs—and stacked SOP, which is similar to parallel board fabrication. This workshop reviews the latest R & D and manufacturing status of each of the three electronic technologies around the world. It will also attempt to compare and contrast SOC, 3D stacking, SIP, SOP and MCM. For registration and continuously updated info, visit: www.prc.gatech.edu/3s |
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INFRASTRUCTURE & ENGINEERING SERVICES Wafer
Level 100 Micron Pitch Flip Chip with Lead-free Bumping PRC
Installs ESPEC Thermal Cycling Chamber The Center is currently in need of a vibration table set-up to fit the system. This need represents an opportunity for in-kind contribution for membership to the PRC. |
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Georgia
Institute of Technology Packaging Research Center
- An NSF Engineering Research Center -
Leading the SOP & Nano Packaging Paradigms in Partnership with Global
Industry
For further info, please visit: http://www.prc.gatech.edu
PH: 404-894-9097, FAX: 404-894-3842 • 813 Ferst St., MaRC Bldg. 351 • Atlanta, GA 30332-0560
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