Georgia Institute of Technology Packaging Research Center An NSF Engineering Research Center Leading the SOP & Nano Packaging Paradigms in Partnership with Global Industry
	e-newsletter Vol. 1, Issue 4 – May 2004

PRC Proposes to Define SOP from 3D, SIP, MCM and SOC
The System-on-Package (SOP) being pursued by the PRC is different from [others] and offers advantages over MCM, 3D packaging and SIP. The 3D packaging is a general concept of interconnecting discrete layers, after fabrication, electrical test and repair, if necessary to yield of individual layers. The 3D, in the past, is also used to describe stacking of similar chips such as DRAMS. MCMs , on the other hand, simply interconnect ICs or components horizontally or in 2D. The SIP goes beyond and stacks similar or dissimilar ICs and it may even embed both actives and passives. But the passives in SIP are typically currently-available discrete, thick and bulky components. The SIP stacking can be either die stacking or package stacking. The SOP goes one step further in the ultimate 3D integration of components in thin film form at microscale in the short term, and nanoscale in the long term. For example, decoupling capacitors can be several millimeter-thick-discrete ceramic capacitors , made of multilayer thick film technologies, or they can be one layer of ultra thin film technologies that are about a micron or less in thickness. Embedding of mm-thick currently available discrete multilayer thick film capacitors is typically done in SIP, whereas in the latter, the ultra-thin film are integrated. But SOP is more than capacitors; it is filters and antennas. It is also embedding of thin-film optical components such as detectors, lasers, waveguides, etc. PRC defines SOP as Moore ’s Law for system integration akin to Moore ’s Law ICs. SOP thus is a system technology in contrast to SIP, SOC and MCM as being sub system technologies.

Call For Papers – Second International Workshop on Nano Bio-Electronic Packaging - March 2005
The PRC, in partnership with the IEEE-CPMT society and NEMI, announces the second nano workshop to be held in Atlanta in March 2005. This follows a very successful first international workshop recently held in Atlanta where over 80 U.S. and international attendees from academia, industry and national laboratories participated. The second workshop is also expected to be well attended and will host a number of scientists and professors at the forefront of nano technology. The workshop will be chaired by Professors Rao R. Tummala and Z.L. Wang at Georgia Tech, both prominent figures in electronics packaging and integration technologies at the university.

The first day will be devoted to a plenary session featuring several keynote speakers. More information will be provided at a later date. The following day will include technical sessions on the following:

Abstract submission: Please send your title and a 300-word abstract, electronically, to nbep@ee.gatech.edu by October 15, 2004 . For further information, online registration, and program updates, we invite you to periodically visit the PRC website: www.prc.gatech.edu/nanobiopack

RESEARCH ADVANCES & INNOVATION

The Digital Systems Packaging alliance is focused on the development of next generation technologies for the packaging of future microprocessors and integrated systems. The goals of the alliance are consistent with the International Technology Roadmap on Semiconductors (ITRS) with 200W power consumption, 0.7V supply and 10GHz frequency in the near term and 288W power consumption, 0.4V supply and 28GHz in the long term. The research areas in the alliance consist of design, fabrication, known good die, electrical test, reliability and thermal management. In this newsletter, the focus is on design and test.

EDA Tools for Signal and Power Integrity
The alliance has been involved in the development of the next generation design tools for signal and power analysis during the last 5 years. These tools are now mature and can be applied to complex packages for analyzing chip power distribution, package power distribution, macro-modeling of linear distributed interconnect networks, black box modeling of non-linear drivers, statistical analysis and extraction of noise current signatures. These tools have been calibrated with measurements. The recent developments in the EDA area are:

• Release of BEMP 3.0
  The Broadband Efficient Macro-modeling Program (BEMP) can be used to generate spice compatible macro-models of distributed interconnect networks. BEMP uses rational function approximation of the frequency response and guarantees stability and passivity by construction. The output is a spice netlist that can be used in a standard circuit simulator such as HSpice.
• Black box modeling of non-linear drivers
  IBIS, which is the industry standard for the representation of non-linear drivers, generates inaccuracy in the modeling of fast I/O drivers. The method developed, which is an extension of the work at University of Torino, Italy, provides accuracy similar to transistor level drivers and a speed-up of 10X – 100X as compared to transistor level drivers. This method uses a combination of spline functions, finite time difference and artificial neural networks to approximate the response of I/O drivers. The output is a spice netlist that can be used in a standard circuit simulator such as HSpice.
• Noise current signatures
  Power supply noise estimations in high speed systems require the accurate representation of the current source. The method developed uses a combination of wavelets and generalized pencil of function method to approximate the current source from measurements. The output is a spice model compatible with standard circuit simulators such as HSpice. This method has been benchmarked with measurements on a 750MHz system from SUN.
• Desperado
  DESign of PowERAware Distribution and Optimization is an on-chip tool for the analysis of multi-layered power distribution networks. This tool uses a two step process for simulating power supply noise namely, 1) extraction of the RLGC parameters using analytical models and 2) simulation using the finite difference time domain (FDTD) method. This method includes the silicon substrate resistivity during the extraction process. In a recent study, a 6mm x 6mm chip with 6 metal layers was simulated with ~5M nodes and ~22M RLGC elements to compute the power supply noise distribution across an entire chip.

Electronic Bandgap Structures (EBG) for Noise Isolation in Mixed-signal Systems
A major problem in mixed signal systems is noise isolation between the digital and analog/RF circuits. For systems with a single power supply, the noise coupling can be substantial through the power distribution network. This coupling increases as the processor speeds increase. In this research, by patterning the ground plane, bandgap structures have been created which provide an isolation of better than -100dB between the digital and RF circuits. The bandgap is tunable and requires no additional layers in the package or board. The inherent resistive loss in the structure helps damp the cavity resonances and radiation. This structure can currently be applied to sub-systems operating in the 1 – 10GHz range and has been implemented on WLAN cards for the 11802.11b/g/a applications.

Development of Measurement Based Time Domain Models
A new method has been developed for the extraction of transmission line parameters directly from one-port TDR measurements. These models include the frequency dependent RLGC behavior of transmission lines and are compatible with standard circuit simulators such as HSpice. These non-physical RLGC models ensure causality and provide good accuracy for transmission lines operating in the high frequency range. This method has been used to characterize package and silicon transmission lines with varying material parameters and has been applied for the design of wafer level packages supporting >5Gbps of data transmission.

PUBLICATIONS

Digital Systems Packaging Publications

Journal

• J. Choi, S. Min, J. Kim, M. Swaminathan and W. Beyene, "Modeling and Analysis of Power Distribution Networks for Gigabit Applications", IEE E Transactions on Mobile Computing, pp. Vol. 2 No. 3, Dec 2003.

• Erdem Matoglu, Madhavan Swaminathan, Nam Pham, Daniel N de Araujo, and Moises Cases, "Statistical Signal Integrity Analysis and Diagnosis Methodology for High Speed Systems," To appear in IEEE Transactions on Advanced Packaging, 2004.

• V. Govind, S. Dalmia and M. Swaminathan, "Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates", IEEE Transactions on Advanced Packaging, pp., Vol., 2004.

• S. H. Min and M. Swaminathan, "Construction of broadband passive macromodels from frequency data for distributed interconnect networks", To appear in the IEEE Transactions on Electromagnetic Compatibility, 2004.

• M. St. Laurent and M. Swaminathan, “Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors”, IEEE Transactions on Advanced Packaging, pp., Vol., 2004.

• M. Swaminathan, J. Kim, I. Novak and J. Libous, “Power Distribution Networks for System on a Package: Status and Challenges”, To appear in IEEE Transactions on Advanced Packaging, 2004.

Conference Papers  

• S. H. Min and M. Swaminathan, “Construction of Broadband Passive Macromodels from Frequency Data for Simulation of Distributed Interconnect Networks”, Proceedings of the Internal Symposium on Electromagnetic Compatibility, Zurich, Switzerland, Feb. 2003.

• W. Beyene, C. Yuan, J. H. Kim and M. Swaminathan, “Modeling and Analysis of Power Distribution Networks for Gigabit Applications”, Proceedings of the International Symposium on Quality Electronic Design, San Jose, CA, Mar. 2003.

• Bavisi, S. Dalmia, V. Sundaram, G. White and M. Swaminathan, "A 3G/WLAN Voltage Controlled Oscillator with High Q Embedded Passives In High Performance Organic Substrate", Proceedings of the Asia Pacific Microwave Conference, Seoul, S. Korea, Nov. 2003.

• Bavisi, S. Dalmia, V. Sundaram, G. White and M. Swaminathan, "A 802.11a WLAN Oscillator with High Q Embedded Passives on Laminate-Type Organic Package", Proceedings of the Topical Conference on Wireless Communication Technology, Honolulu , Hawaii, Oct 2003.

• B. Mutnury, M. Swaminathan and J. Libous, "Macro-Modeling of Non-Linear I/O Drivers using Spline Functions and Finite Time Difference Approximation", Proceedings of the 12th Topical meeting on Electrical Performance of Electronic Packaging, Princeton, NJ, Oct. 2003.

• B. Mutnury and M. Swaminathan, "Macro-Modeling Methodology For Weakly Non-Linear Digital Drivers", Proceedings of the Signal Propagation on Interconnects Workshop, Sienna, Italy, May 2003.

• E. Matoglu, M. Swaminathan, D. Arujo, N. Pham and M. Cases, "Design Space Exploration of High-Speed Busses Using Statistical Methods", Proceedings of the 12th Topical meeting on Electrical Performance of Electronic Packaging, Princeton, NJ, Oct. 2003.

• J. Mao, M. Swaminathan, J. Libous and D. O'connor, "Effect of Substrate Resistivity on Switching Noise in On-chip Power Distribution Networks", Proceedings of the 12th Topical meeting on Electrical Performance of Electronic Packaging, Princeton, NJ, Oct. 2003.

• R. Mandrekar, M. Swaminathan and S. Chun, "Extraction of Current Signatures for simulation of Simultaneous Switching Noise in High Speed Digital Systems", Proceedings of the 12th Topical meeting on Electrical Performance of Electronic Packaging, Princeton, NJ, Oct. 2003.

• V. Govind, S. Dalmia, J. Choi and M. Swaminathan, "Design and Implementation of RF Subsystems with Multiple Embedded Passives in Multi-Layer Organic Substrates", Proceedings of RAWCON, Boston, MA, Sep. 2003.

• J. Mao, W. Kim, S. Choi, M. Swaminathan, J. Libous and D. O’Connor, “Electromagnetic Modeling of Switching Noise in On-Chip Power Distribution Networks”, Proceedings of the International Conference on Electromagnetic Interference and Compatibility (INCEMIC), pp. 47-52, Chennai, India, Dec. 2003.

• Woopoung Kim and et al., “Electrical Design of Wafer Level Package on Board for Gigabit Data Transmission,” 5th Electronics Packaging Technology Conference , Singapore, Dec. 2003.

• Woopoung Kim, R. Madhvan, and M. S aminathan, "Interconnects Modeling and Design for high speed information and communication,” PIERS 2004, Pisa, Italy, Mar. 2004.

• R. Mandrekar and M. Swaminathan, "Wavelet Based Nonparametric Regression Approach for De-noising and Modeling of Transient Switching Noise Measurements", 5th Electronics Packaging Technology Conference, Singapore, Dec. 2003.

• R. Mandrekar, M. Swaminathan and S. Chun, "Application of Wavelets and Generalized Pencil-Of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching Noise", 17th International Conf. of VLSI Design, Bombay, India, Jan. 2004.

• J. Choi, J. Kim, M. Swaminathan, W. Beyene and C. Yuan, “Efficient Hybrid Methodology for Analyzing Power Distribution Networks in High-Speed System,” Progress in Electromagnetics Research Symposium (PIERS), Honolulu, Hawaii, Oct. 2003.

• M. Swaminathan, “Modeling of Chip and Package Power Distribution for Gigascale Integration”, Plenary Session, PIERS, Pisa, Italy, Apr. 2004.

AWARDS & RECOGNITION

Outstanding Intel Student Paper Award
R. Mandrekar, M. Swaminathan and S. Chun, "Extraction of Current Signatures for simulation of Simultaneous Switching Noise in High Speed Digital Systems", Proceedings of the 12th Topical meeting on Electrical Performance of Electronic Packaging, Princeton, NJ, Oct. 2003.

Best Paper Award
J. Mao, W. Kim, S. Choi, M. Swaminathan, J. Libous and D. O’ Connor, “Electromagnetic Modeling of Switching Noise in On-Chip Power Distribution Networks”, Proceedings of the International Conference on Electromagnetic Interference and Compatibility (INCEMIC) , pp. 47-52, Chennai, India, Dec. 2003.

Infrastructure Award from IBM
The digital alliance was recently awarded an equipment grant from IBM that has substantially enhanced the computing capabilities of the center. The generous grant includes a 16 CPU X-Series cluster with 2.8GHz processors that can be configured for parallel processing. The cluster will be used for the electromagnetic analysis of large packaging structures using the design tools developed within the center. The grant was possible due to the collaboration between Moises Cases ( IBM ) and Madhavan Swaminathan (GTech) over many years.

Distinguished Service Award
On April 23, 2004, Russell D. Dupuis received the University of Illinois at Urbana-Champaign College of Engineering Distinguished Service Award in a ceremony at the University of Illinois at Urbana-Champaign.

Best Paper Awards
Given at the 9th International Symposium on Advanced Packaging Materials (Atlanta)

Interconnection Materials
”Recent Advances of Interconnection Technologies using Anisotropic Conductive Films in Flat Panel Display Applications” - Itsuo Watanabe, Tohru Fujinawa, Motohiro Arifuku, Masaki Fujii, Yasushi Gotoh - Hitachi Chemicals

Manufacturing and Reliability
“Topside Cooling Microwave Devices By Replacing Air-Bridges With Su-8 Polymer Bridges” - Joshua Wright, R. Fillion, D. Shaddock, L. Meyer - General Electric Global Research & Development

Passives
“Development of high K embedded capacitors on printed wiring board using sol-gel and foil transfer process” - Isaac Robin Abothu, P. Markondeya Raj, Devarajan Balaraman, Swapan Bhattacharya, Michael D. Sacks and Rao R. Tummala - Georgia Tech  

“Integrated Resistor Material with Zero Temperature Coefficient of Resistance and High Stability” - Fan Wu, James E. Morris - SUNY Binghamton/Portland State University

New Technologies
“Dielectric Characteristics of Complex Composite Systems Containing Interphase Regions” - Michael Todd, Frank Shi - Loctite/UC Irvine

Poster Session
“A Novel Technique for Lead-Free Soldering Using Variable Frequency Microwave (VFM)” - Kyoung-sik Moon, Yi Li, Jianwen Xu and C.P. Wong - Georgia Tech

“Formation of Self Assembled Monolayer (SAM) on Metal Surfaces for High Performance Anisotropically Conductive Adhesives” - Yi Li, Kyoung-sik Moon, C. P. Wong - Georgia Tech

“Effects of Nano-Sized Particles on Electrical and Thermal Conductivities of Polymer Composites” - Lianhua Fan, Bin Su, Jianmin Qu, C. P. Wong - Georgia Tech  

Advanced Substrate Technologies - Development and Characterization
“Tuning of Electric Artworks of Printed Circuit Boards to Reduce Warpage” - Parsaoran Hutapea, Joachim L. Grenestedt - Lehigh University

Flip Chip and Underfills
“Influence of Nanosilica on Composite Underfill Properties in Flip Chip Packaging” - "Yangyang Sun, Zhuqing Zhang, C.P. Wong - Georgia Tech

EDUCATION

PRC is Awarded a “Research Experience for High School Teachers – Site” Grant by NSF
The National Science Foundation recently awarded the PRC to develop and implement a summer research experience program for the metro Atlanta high school physics teachers during the next three summers. The program, called Summer Teacher Experience in Packaging Utilizing Physics (STEP-UP), will provide training for 36 teachers in modern physics concepts, their applications to engineering, and their relevance to today’s microelectronic technologies through a three week course and a five- week research experience. Professors Tummala, Kohl, Bidstrup-Allen, Chang, Adibi, Swaminathan, Joshi, Qu and Wong will each mentor a teacher and provide him/her with an opportunity to work in their state-of-the-art microelectronic packaging research laboratories. In addition to the courses and research experience during their stay at the Center, the teachers will attend four workshops to prepare research-based curriculum materials for classroom implementation during their next academic year. Upon completion of the program, it is anticipated that the teachers will have more confidence in teaching physics and connecting it to engineering and technology applications and thus be better able to instill an interest in their students towards careers in engineering.

EVENTS

Visit the PRC to Know about the PRC’s Openhouse on the Emerging and Disruptive Packaging Technologies for the Next Decade

The PRC is seeking industry partners to collaborate on the emerging and disruptive packaging technologies for the next decade, including:

• PCB and Microvia & Global Interconnect for Ultra-High Density, High Frequency Digital Packaging

• Embedded RF Packaging (Embedded Functions, Vertical, Multi-Layer Integration, & MEMS)

• Chip-to-chip Optoelectronics Packaging

• Flip chip and Wafer Level Packaging and Assembly with underfill and Pb-free solders: Design, board Fabrication, Test, Burn-In & Reliability

• Highly Integrated and Multi-function SOP Packaging including Nano Bio-electronics Packaging

Therefore, the PRC plans to host an “open house” on Wednesday, June 16 th at Georgia Tech’s campus in Atlanta . The open house will provide participants with an overview of PRC’s research activities, tour of research facilities, and discussion on ways to collaborate. The open house is intended for technical managers, leaders, and executives from industry research & development (R&D) departments interested in learning more about PRC, system-on-package (SOP), and potential collaboration opportunities. More details, including an agenda, and registration, are available at http://www.prc.gatech.edu/news_events/ganextgen2004.htm

INFRASTRUCTURE & ENGINEERING SERVICES

PRC’s “Engineering Services” Enables Georgia Economic Development
Working closely with Mr. Henry (Hisao) Noguchi, Vice President of Harima USA, INC., the PRC has enabled the start-up of a new Harima subsidiary solder paste company called Harimatec Inc, located in Duluth Georgia.

In an unprecedented effort, and as part of the new "industry focused" service offerings of the PRC, the infrastructure team is utilizing the assembly prototype laboratory to provide an early manufacturing environment enabling Harimatec to meet immediate US demands for the production of various solder pastes for US electronics industry. This effort was strategic to Harima’s decision to locate a manufacturing facility in the local Atlanta region. Harima plans to transition out of the PRC facility and into their new production facility by the beginning of 3rd quarter 2004 when Harima opens their first US based solder paste manufacturing plant. Product information and requests for solder paste can be directed to Mr. Noguchi at Harima USA (noguchi@harimausa.com).

Georgia Institute of Technology Packaging Research Center
- An NSF Engineering Research Center -
Leading the SOP & Nano Packaging Paradigms in Partnership with Global Industry

For further info, please visit: http://www.prc.gatech.edu

PH: 404-894-9097, FAX: 404-894-3842 • 813 Ferst St., MaRC Bldg. 351 • Atlanta, GA 30332-0560

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