DIRECTOR'S CORNER
PRC has begun the transition from NSF-centric to Global Industry-centric. Over the last 11 years, the PRC has been a National NSF Center focusing on an integrated approach to Research, Education and Industry Collaboration in the SOP technology paradigm. During this period, it had pioneered SOP technology, developed extensive expertise, facilities and collaborated with more than 150 companies around the globe, transferring parts of SOP technologies to them. It has also made Packaging as an academic subject for the first time, with courses, curricula and textbooks, and graduating around 575 students.

The PRC transition is taking place in research with newer emerging technologies such as embedded actives and passives, nano-bio-info technologies, and in research staff to address these newer technologies and to work with industry more effectively.

The PRC is now very Industry-centric and Global. It works with global industry in exploring newer technologies at project level, and in addition, it is setting up large thematic, program level consortia on a variety of topics such as Design Tools, Embedded Actives and Passives, Thermal Interface Materials, Mixed Signal Test, Nano Materials and Packaging, etc. Given its breadth of know-how from Design to Prototype, on one hand, and complete cleanroom facilities on the other hand, it is also embarking on large company contracts to demonstrate the next generation of SOP-based modules.

To make this transition, it has set up a new management team with Prof. Madhavan Swaminthan as Deputy Director, Dr. Mahadevan Iyer as Research Director, Dean Sutter as Finance and Infrastructure Director and three Assistant Research Directors: Dr. Raj Pulugurtha, Dr. Chong Yoon and Venky Sundaram. In addition, it continues with Research Faculty Directors, Prof. Swaminathan for SOP Design, Prof. John Papapolymerou for RF SOP, Prof. Gee-Kung Chang for Opto SOP, Prof. C. P. Wong for Wafer Level Packaging and Assembly.

The PRC is thus reinventing itself and beginning to grow in newer research areas and in new ways to collaborate with the global industry.

Prof. Rao R. Tummala
Endowed Chair Professor
Director of PRC, Georgia Tech

INDUSTRY CONSORTIA NEWS

GT-PRC Seeks Company Collaborations in Next Generation of Embedded Actives & Passives (EMAP) for Electronics Convergence
Consortium Launch Planned for July 1, 2006

The Georgia Tech Packaging Research Center (GT-PRC) organized a focused workshop on EMAP held on Feb. 8, 2006 at Georgia Tech. Thirty companies from Systems, Semiconductors, Materials, Packages, Boards and Tools, attended the workshop.

The overall objective of this workshop was to set up an industry consortium on next and future generations of EMAP technologies at GT-PRC, with its proposed Silicon partner, IME in Singapore and Quality and Reliability partner, Calce of University of Maryland. Toward this goal, Georgia Tech presented a review of the state of the art of embedded actives and passives technologies preceded by five invited keynote talks by Dr. Zaher Bardai (Raytheon), Dr. Grit Sommer (Infineon), Sampath Karikalan (Broadcom), Gerd Riha (EPCOS), and Ray Fillion (GE).

These industry talks highlighted both the status and the future needs in embedded actives and passives as well as in SIP/SOP technologies for system integration from industry perspective.

Over the past 10 years, GT-PRC has developed world class expertise and capabilities in mixed signal design and test, multi-function SOP substrate with embedded micro and nanoscale thin film embedded actives and passives, advanced interconnection techniques, thermal management and reliability modeling and design.

Georgia Tech and its partners described seven barrier technologies for future EMAP-based digital convergent systems. It also proposed solutions for discussion with industry members that attended the workshop.

The seven major EMAP technologies identified at the workshop are:
1. EMAP electrical design
2. Embedded thin film digital and RF passives in organic substrates
3. Ultra thin core substrate
4. Ultra thin silicon
5. Ultra fine-pitch chip-last interconnections with chip-first benefits
6. Thermal management solutions
7. Design EMAP for quality and reliability

Many companies expressed interest in the proposed consortia and its topics. A short white paper covering the details of the seven research elements will be sent to companies that expressed interest in EMAP, at end of March or early April. Follow-up discussion with companies will take place in Spring 2006. A second meeting is planned for June 20th at Georgia Tech. The consortium is set to launch on July 1, 2006.

Interested companies are encouraged to contact Prof. Rao Tummala (rao.tummala@ece.gatech.edu, 404-894-9097), Chong Yoon (cyoon@ece.gatech.edu, 404-385-6231), or Mahadevan Iyer (mahadevan.iyer@ece.gatech.edu, 404-385-7302).

RESEARCH ADVANCES & INNOVATIONS

First 100 Micron Pitch IC-Package Flip Chip Interconnection Demonstrated
GT-PRC demonstrated the first lead-free solder with underfill at 100µm pitch 2cm chips. GT-PRC designed, developed and demonstrated 100µm pitch, lead-free bump materials, underfill and substrate processes, as well as 1,000 cycle reliability. Assembly process parameters with underfill have been optimized. The size of the chip was 20mm x 20mm, and more than 3,000 Sn/Cu lead-free solder balls in three rows were fabricated as a peripheral array. The stand-off height for the solder, before reflow, was between 35-50µm. An advanced substrate technology with the same 100µm pitch, with medium-CTE substrate was fabricated to demonstrate the assembly. By accurately controlling the alignment, a high yield of ultra-fine-pitch flip-chip assembly process was attained. An accelerated thermal cycle test (-40 ~ 125°C) showed that more than 95% of the daisy chains survived after 1,000 thermal cycles. Contact C. P. Wong (cpwong@mse.gatech.edu) or Yeong Kim (yeong.kim@ece.gatech.edu) for further information.

PRC Addresses Thermal Management Solutions of Embedded Actives and Passives
Recent research in the thermal management group has been concerned with laying the foundation for the EMAP consortium. Basic analyses of the heat that can be removed by convection, radiation, and conduction from a cell phone-sized object have shown that, for a sustained power consumption of 4 watts and higher, forced convection heat rejection to the ambient may be needed. Various initial concepts for removing heat from embedded actives are being developed as a prelude to the EMAP program. These methods include internal conduction by vias and spreaders, micro heat pipes, and pumped microchannel loops (both single and two-phase). In addition, the thermal time response of a handheld in use has been modeled as part of determining whether phase change material packets could be used for thermal load smoothing. Contact David Gerlach (dg179@mail.gatech.edu) or Yogendra Joshi (yogendra.joshi@me.gatech.edu) for further information.

PRC Embeds MMICs in Multilayer LCP Substrate
A Microwave Monolithic Integrated Circuit (MMIC) has been successfully embedded into a multilayer LCP substrate. Low melting temperature LCP layers (285° C) are used to adhere generally thicker high melting temperature core layers (315° C) to create a homogeneous LCP package stack up. Since LCP comes commercially in 1, 2, and 4 mil thicknesses, the layers required stacking to achieve the necessary thickness and cavity topology to encase an active device. A cavity was formed above the chip so that the wire bonds have sufficient space to connect from the chip pads to the feeding transmission lines. This vertical clearance (on the order of 100 m) is also important since, in the final topology, the bypass capacitor and chip will be elevated slightly by an electrically conductive cured silver paste that connects the components to the RF ground plane. The 12-26 GHz LNA was first measured without the packaging layers, and then after the chip was packaged with an LCP thermocompression bonding process. The results show that the gain produced by the chip after the packaging process (45 minutes at 285° °C with ~300 psi tool pressure) is nearly the same as that before the packaging process. The effects of the package’s dielectric discontinuity and the heat/tool pressure of the bonding process are thus shown to have minimal effects on the embedded/packaged MMIC performance. Contact Profs. Manos Tentzeris (etenze@ece.gatech.edu) or John Papapolymerou (papapol@ece.gatech.edu) for further information.

Simultaneous Electrical/Mechanical Optimization Tools for 3D Multilayer RF Modules
Statistical tools like Design of Experiments (DOE) and Response Surface Methods (RSM) have been combined with full-wave time-domain electrical and FEM mechanical simulations to perform, for the first time, the simultaneous optimization of the electrical and mechanical performance of 3D RF integrated modules with embedded passives/actives. This is the first ever design and optimization tool that fully includes all process/fabrication "six-sigma" variations for the accurate design of multilayer (ceramic and organic) and wireless modules. It could revolutionize the electromagnetic and mechanical co-design of embedded passives and actives in multiband systems of the future. The benchmarking geometry was a stacked patch antenna integrated in a sandwich structure made of composite laminates and Nomex® honeycomb. The antenna is electromagnetically modeled in time domain and it is found that, for the chosen geometry, the honeycomb structure improves the gain of the antenna without affecting the bandwidth. The structure is then optimized using the same experiment that integrates both the electrical and mechanical parameters of the system. The simple factorial design is very simple to implement and gives a clear understanding of the system behavior, including the interaction between the mechanical changes and electrical performance thus allowing the engineer to integrate, for the first time, both the electrical and mechanical features of the system in the same optimization technique. The experiment was very simple to implement and provided a thorough understanding of the issues to be confronted in the optimization process. Contact Dr. Daniela Staiculescu (dstaiculescu@gmail.com) or Prof. Manos Tentzeris (etentze@ee.gatech.edu) for further information.

PRC Designs and Develops Ultra Wideband Antenna
The objective of the UWB antenna design is the design and development of light, compact antennas with omni-directional patterns. Several designs have been fabricated and measured on 100 µm thick LCP substrate with omni-directional patterns and constant gain around 2 dBi in the whole UWB range (3.1-10.6 GHz). The tested prototypes are compact (28mm x 32mm) and can be easily integrated with active components and be used for several UWB applications for personal and mobile communication systems. Contact Profs. John Papapolymerou (Papapolymerou@ece.gatech.edu) or Manos Tentzeris (etentze@ece.gatech.edu) for further information.

PRC Develops Accurate Eye Diagram Simulations, Conserving Causality and Switching Noise Reduction Using Electromagnetic Bandgap Structures
For signal integrity analysis of interconnects, ensuring passivity has been a major problem, but it has been solved. For the first time, GT-PRC was able to generate a method that ensures causality, which is another fundamental physical property. Based on this method we showed the improvement in accuracy for eye diagrams of 1000 switching I/O lines in an IC package. In addition, to reduce the switching noise, new electromagnetic bandgap (EBG) structures have been developed with improved attenuation and stopband properties. These structures practically suppress all the power supply coupling between RF and digital domains (for example, a GSM application) in a mixed-signal SOP design. Contact Ege Engin (engin@ece.gatech.edu) or Madhavan Swaminathan (madhavan.swaminathan@ece.gatech.edu) for further information.

PRC Extends its SOP Concept to Nano-Bioelectronics
The unique properties possessed by nano-structured materials facilitate fabricating advanced nanobio-electronic sensors with superior sensitivity and specificity. ZnO nanobelts/wire and carbon nanotubes exhibit outstanding charge-transport characteristics, high surface area, ultra sensitive electrical behavior towards biomolecule attachment which make them ideal for fabrication of nanobioelectronic sensors. Recently, we fabricated nanobio sensors by biofunctionalizing ZnO nanobelts/wire and multi-walled carbon nanotubes (MWNTs). The device characteristics of biosensing nanobelts were measured and the shift in the electrical impedance was conformed. Further, we demonstrated the electronic detection of starch hydrolysis using ZnO nanobelts/wire. The capabilities of these sensitive nano devices will be utilized for early detection of cancer; traces of toxins and pathogens; and enzyme-catalyst based reactions. These nanobioelectronic devices will be integrated both in the organic and Si platforms to demonstrate SOP based nanobio sensors. Contact Drs. Janagama Goud (jgoud@ece.gatech.edu) and Mahadevan Iyer (mahadevan.iyer@ece.gatech.edu) for more info.

PRC Develops End-to-end Optical Interconnect System Integration on FR-4 Boards at 10-40 Gbps
GT-PRC has demonstrated an end-to-end optical interconnect System-on-Package (SOP) at 10 Gbps using a directly modulated DFB edge emitting laser at 1310 nm and 1550 nm wavelengths. The DFB lasers are end-coupled to an optical waveguide at the transmitter block. After transmitting through polymer waveguide, the optical signals are coupled to a PiN PD by a 45° WG end mirror at the receiver block. Several silicon chips are integrated on this FR-4 board including a laser driver for driving laser diodes, TIA and Limiting Amplifier (LA) for amplifying detector signals. The system is tested with A Pseudo-random bit stream input via an SMA connected to an on board coplanar waveguide (CPW) transmission line. The electrical output from the Limiting Amplifier is analyzed by a digital communication analyzer via an output CPW and SMA edge connector. Contact Fuhan Liu (fliu@ece.gatech.edu) or Prof. Gee-Kung Chang (gkchang@ece.gatech.edu) for further information.

Large Panel 45° Micro-mirror Integration
The optical beam bending element, 45° micro-mirror, is one of the key components for integrated opto-electronics systems, which is attracting much attention from industry. It is used in optical circuits to steer the beam propagation direction by 90 degrees for laser-to-waveguide, waveguide-to-photodetector, and also for Z-direction optical interconnections between two waveguides in different substrate layers. GT-PRC has developed a simple, innovative, low-cost, and efficient method to fabricate 45° micro-mirrors at the end of polymer waveguides. This method is based on a tilted UV beam lithography with incident angle of 45° inside the optical polymer. Micro-mirrors and waveguides are formed simultaneously during the photolithographic process. It is suitable for large panel circuits such as optical back-plane fabrication. This process was carried out in a regular board fabrication facility without requiring special materials, equipment or extra cost. Both facet-up and facet-down integrated micro-mirrors with 45° angle or greater have been demonstrated. Contact Fuhan Liu (fliu@ece.gatech.edu) or Prof. Gee-Kung Chang (gkchang@ece.gatech.edu) for further information.

PRC ACCOUNTING AND FINANCE SUPPORT STAFF

Traci Walden

Christine Baker

Dean Sutter

Carl Rust

Mahadevan Iyer

The GT-PRC announces the addition of Ms. Traci Walden as Accounting and Finance Manager, and Ms. Christine Baker as Accountant who will assist with the responsibilities for Accounting and Finance Support. The focus of this new team is to improve support to industry and center staff by streamlining systems, eliminating redundant efforts and implementing process improvements. As part of a continued commitment to our industry partnerships, two highly qualified individuals have been appointed to head that effort; Mr. Dean Sutter, Associate Director of Infrastructure and Finances, joined the team in 1995, and Dr. Mahadevan Iyer, Research Director, joined us in Fall 2005, coming from the Institute of Microelectronics (IME) in Singapore.

Carl Rust, former Associate Director who fostered industry partnerships, recently left to pursue a new career role at Georgia Tech, focusing on industry relationships. We express thanks and best wishes to him in his new endeavors.

PRC TEAM MEMBER HIGHLIGHT

Dr. Mahadevan Iyer
Dr. Mahadevan Iyer is GT-PRC's new Research Director, whose position was created to identify, develop and direct strategic research programs.

Dr. Iyer's expertise includes the design and development of microelectronic circuits, design and System-in-Package (SIP) development for mixed signal, optoelectronics, MEMS and bio-electronic applications. His expertise was gained through more than 20 years of research and development. His publications include 150 papers and his awards are numerous, including the prestigious Commonwealth award (U.K.); the John Guest Philips award from Loughborough University of Technology (U.K.); and four Best Paper awards in International conferences. He has 12 U.S. patents awarded.

AWARDS & RECOGNITIONS

Faculty and Staff Awards

Prof. Madhavan Swaminathan, ECE, PRC Deputy Director Elected an IEEE Fellow for contributions in design tools, design methodologies and electromagnetic interference control for power delivery in digital and mixed-signal systems.

Prof. Thomas Gaylord received the "Esther Hoffman Beller Medal" presented in Oct. 2005 and the "Microelectronics Advanced Research Corporation Inventor Recognition Award" for inventive contributions in support of MARCO sponsored research, in February 2006.

Prof. Emmanouil M. Tentzeris has been named as the recipient of the 2006 IEEE MTT-S "Outstanding Young Engineer of the Year Award." Dr. Tentzeris will be recognized for his innovation in the development of multi-resolution CAD tools and the design and optimization of 3D RF modules in ceramic and organic substrates up to mm-wave frequency range. Award to be presented at the annual IEEE MTT-S International Microwave Symposium in San Francisco, June 2006.

Profs. Madhavan Swaminathan and Gee-Kung Chang received IBM Faculty Awards from the IBM Austin Center for Advanced Studies. Dr. Swaminathan’s award will support his project, "Design, Fabrication, Characterization, and Test of Nano-Materials for Embedded Decoupling in Mid-Frequency Range for Server Applications," and Dr. Chang’s award will support his work in "High Speed Optical Interconnects for High Throughput, Low Latency Server Systems."

Prof. C. P. Wong, Regents' Professor and the Charles Smithgall Institute Endowed Chair, School of Materials Science & Engineering, Georgia Institute of Technology, received the Georgia Tech 2006 "Outstanding Ph.D. Thesis Advisor Award" in February 2006.

GT-PRC director, Rao Tummala, recently awarded the following researchers for their outstanding work:

Dr. Raj Pulugurtha, for the most proposals and publications.
Mr. Venky Sundaram, for the most integrative process research and teamwork.
Dr. Ege Engin, for the fastest start and program management in PRC.
Dr. Chong Yoon, for the most effective international collaborations.

Jinwoo Choi and Prof. Madhavan Swaminathan received SRC Inventor Recognition Award for "A Novel Electromagnetic Bandgap (EBG) Structure for Isolation in Mixed-Signal Systems", J. Choi, V. Govind, M. Swaminathan, SRC TECHCON ‘05, Oct. 2005.

Best and Outstanding Paper Awards

"Liquid Crystalline Polymer Based RF/Wireless Components for Multi-Band Application," S. Dalmia, V. Sundaram, G. White, M. Swaminathan, IEEE Electronic Components and Technology Conference, 2004.

"The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade," Rao R.Tummala, Madhavan Swaminathan, Manos M. Tentzeris, Joy Laskar, Gee-Kung Chang, Suresh Sitaraman, David Keezer, Daniel Giudotti, Zhaoran Huang, Kyutae Lim, Lixi Wan, Swapan K. Bhattacharya, Venkatesh Sundaram, Fuhan Liu, P. Markondeya Raj, May 2004

"Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates," V. Govind, S. Dalmia and M. Swaminathan, IEEE Transactions on Advanced Packaging, 2004

"High Frequency Characteristics of Supercapacitive Nanocomposite Thin Films and Their Suitability for Embedded Decoupling," 6th Electronics Packaging Technology Conference (EPTC 2005), Dec., 2005, Singapore; P.Markondeya Raj, D. Balaraman, V. Govind, L.X. Wan, R. Abothu, R. Gerhardt, S. Bhattacharya, M. Swaminathan and R. Tummala, Georgia Institute of Technology, USA.

"Design, Simulation and Measurements of High-Speed Embedded Decoupling Capacitors for Multi GHz Packages/PCBs," International Conference on Electronic Packaging Technology (ICEPT), Shanghai, China, August 2005, Lixi Wan, P. Markondeya Raj, Rao Tummala and M. Swaminathan.

An award was presented to Graduate Research Assistant Wansuk Yun at the 2005 Asia Pacific Microwave Conference held in China. Selected from 309 student papers. Advisor is Madhavan Swaminathan. Paper title was "3D Integration and Characterization Of High Q Passives On Multilayer Liquid Crystalline Polymer (M-LCP) Based Substrate," and the authors are Wansuk Yun, Amit Bavisi, Venky Sundaram, Madhavan Swaminathan, and Ege Engin.

PATENTS & INVENTIONS

Reactive Forming of High K Thin Films
GT-PRC recently filed a patent on a new process for integrating high dielectric constant thin films in organic substrates or organic build-up layers for decoupling applications. Realizing that polymer composites can only address a part of the decoupling problem, industry is currently exploring embedded decoupling with sputtering, paste printing or solution deposition on copper foils followed by a high-temperature treatment with complex heat treatment profiles. The foil is then laminated into organic build-up layers.

GT-PRC’s patent achieves ceramic thin films by simple low temperature hydrothermal or oxidation reactions leading to crystalline high k thin films with very high capacitance density directly on organic substrates. The reactive process can be extended to high temperatures if required, in which case a foil transfer process may be used. The properties with these thin films can satisfy the decoupling requirements for a wide range of high speed digital applications. Contact Raj Pulugurtha (raj@ece.gatech.edu) for further information.

Novel 20-100µm Pitch IC-to-Package Interconnect and Assembly Process for Pb-free Solder, Copper or Gold Stud Bumps
The present invention provides a novel process to extend any interconnection technology with underfill to ultra-fine pitch flip chip process. As the bump height decreases with decreasing the I/O pitch, it is difficult to dispense the high filler-loading underfill into low stand-off height without voids and defects.

GT-PRC is developing a new flip chip process to overcome the underfill and assembly process barriers for ultra-low stand-off fine pitch flip chip interconnections. In this process, the underfill material is first deposited on the fabricated substrate with bond pad surface finish. This can be accomplished by commonly used processes such as spin coating, meniscus/roller coating or curtain coating, or in the case of dry film materials, lamination process. Once the underfill is deposited, the bond pad sites are opened by patterning the underfill material using UV lithography, laser ablation, or plasma/chemical process. At this point in the process, the underfill is in a partially cured or “B-stage” and can be made reflow and fully cure during assembly. An option for this process is to use a filled thermoplastic underfill material that can soften and reflow around the solder joints during assembly.

This new technology creates opportunities to get best mechanical properties, finest pitch with lowest stand-off height, without the problem of dispensing underfills to achieve high reliability. Contact Venky Sundaram (vsunda@ee.gatech.edu), Jui-Yun Tsai (jt05@ece.gatech.edu), Prof. Rao Tummala (rao.tummala@ee.gatech.edu) or Prof. C. P. Wong (wong@ece.gatech.edu) for further information.

Stand-alone Organic-based Passive Devices
U.S. Patent No. 6,987,307; George White, Madhavan Swaminathan, Sidharth Dalmia and Venkatesh Sundaram

Design Methodology with Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structures in Mixed-Signal Systems
U.S. provisional patent application, ID # 3418, filed on April 2005; J. Choi, V. Govind and M. Swaminathan

Multi-band RF Transceivers with Passive Reuse in Organic Substrates
U.S. provisional patent application, ID # 062020-1950, filed on April 2005; A. Bavisi, S. Dalmia, V. Govind, M. Swaminathan, G. White, and V. Sundaram

Integrated Passive Devices Fabricated Utilizing Multi-layer, Organic Laminates
U.S. Patent, ID# 6,900,708, Issued May 31, 2005; G. E. White, M.Swaminathan, V. Sundaram, and S. Dalmia.

SECOND INTERNATIONAL WORKSHOP ON SOP, SIP, SOC (3S) ELECTRONICS TECHNOLOGIES DEADLINES: Titles: May 19, 2006; Abstracts: June 23, 2006 SEND TO: Boyd Wiedenman boyd.wiedenman@ece.gatech.edu September 28 & 29, 2006 • Global Learning & Conference Center at Technology Square • 84 Fifth Street, Atlanta, GA 30308 U.S.A. General Chair: Rao Tummala, Director, Georgia Institute of Technology Technical Chair: Dr. Mahadevan Iyer Program Administrator: Boyd Wiedenman ONLINE REGISTRATION The first workshop, held at Georgia Tech in September 2005, was highly successful featuring industry keynote talks from TI, IBM, Intel, Philips and Skyworks. More than 80 people attended the workshop from Japan, Korea, Europe and the U.S. The focus of the second workshop will add missing elements such as automotive and manufacturing as well as the trade offs between “on-chip” SOC, “on-module” SIP and “on–system” SOP. Since package integration is taking place by means of either on-wafer or on-ceramic LTCC or organic laminate technologies. The tradeoffs between these are also of interest. The SOP paradigm is beginning to take place around the globe particularly in Japan as it changes the current chip-centric SOC methodology to a cheaper, faster-to-market IC-package-system co-design flow. The advantages of the SOP paradigm over SOC appear overwhelming due to SOP’s design simplicity, lower cost and higher system function integration, electrical performance, without the intellectual property issues that dominate SOC. The SOP is also different from, yet complimentary to, 3D packaging and SIP. 3D packaging is typically the stacking of similar, or dissimilar, chips such as DRAMs. The SIP goes beyond to embed both actives and passives but the passives are discrete, thick and bulky components. The SOP goes one step further in the ultimate 3D integration of components in thin film form at microscale, in the short term, and nanoscale in the long term. The SOP focuses on integrating both single function as well as heterogeneous system functions, optimizing ICs for transistors and package for integration of digital, RF, optical, sensor and others. It accomplishes this by build-up SOP, similar to ICs and stacked SOP, and is similar to parallel board fabrication. To summarize, this workshop will review the latest design, R & D and manufacturing status as well as applications of each of the three electronic packaging technologies currently being used around the world. It will also attempt to compare and contrast SOC, 3D stacking, SIP, SOP and MCM. Topics: • Mixed signal design and design tools • Embedded digital integration and modules • Embedded optical integration and modules • Embedded RF integration and modules • Multifunction integration and modules • Materials, processes, fabrication and assembly • Embedded LTC, organic laminate and Si wafer technologies • Mixed signal test • Mixed signal reliability • Stacked ICs and packages • Manufacturing • Applications & products: automotive, computing, consumer and wireless

UPCOMING EVENTS PRC Open House March 13, 2006 MaRC Building Auditorium 813 Ferst Drive, Atlanta, GA 30332 www.prc.gatech.edu/events/openhouse Industrial Advisory Board Meeting March 14-16, 2006 Technology Square Research Building 85 Fifth Street, N.E. Atlanta, GA 30308 www.prc.gatech.edu/events/iab IEEE-CPMT Second International Workshop on SOP, SIP, SOC (3S) Electronics Technologies (See ad below.) September 28-29, 2006 Global Learning & Conference Center at Technology Square 84 Fifth Street, Atlanta, GA 30308 www.prc.gatech.edu/3s IEEE Advanced Packaging Materials Symposium March 15-17, 2006 Georgia Hotel and Conference Center 800 Spring St. NE, Atlanta, GA 30308 www.me.gatech.edu/APM06-IEEE Next Generation Thermal Interface Materials An Industry-PRC Consortia Development Workshop September 27, 2006 MaRC Building Auditorium 813 Ferst Drive, Atlanta, GA, www.prc.gatech.edu/events/tim

Hayato Takeuchi Hiroshi Yamamoto & Masato Iwasaki Jongkuk Hong Mikio Oda PRC WELCOMES VISITING ENGINEERS FROM JAPAN AND KOREA We extend a warm welcome to four engineers visiting from companies in Japan and Korea. Among them are: Hayato Takeuchi, Sony Corporation, Hiroshi Yamamoto, NGK-NTK R&D Center, Japan, Masato Iwasaki, NGK-NTK R&D Center, Japan, Jongkuk Hong, Samsung Electro-mechanics, Seoul, South Korea, and Mikio Oda, NEC Corporation, Jisso and Production Technologies Research Laboratory. Traci Walden Christine Baker Barbara park Janagama Goud Dimitrios Anagnostou NEW PRC TEAM MEMBERS A warm welcome is extended to the following new team members: Traci Walden, Accountant Manager Christine Baker, Accountant Barbara Park, Administrative Coordinator Janagama Goud, Research Scientist in bio-sensor research Dimitrios Anagnostou, Postdoctoral fellow working with Profs. John Papapolymerou and Manos Tentzeris

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RECENT PRC CONTRACTS

Korean Electronics Technology Institute (KETI)
Principal Investigator: Prof. Rao Tummala
Project: Development of Embedded High-k Thin Film Capacitors
Purpose: To develop thin film decoupling capacitors embedded in organic substrate for mobile applications. This project is teamed up with Korean institutes, universities and companies sponsored by the Ministry of Commerce, Industry and Energy (MOCIE) and the Korean Electronic Technology Institute (KETI). It is the first in a series of collaborations in SOP.

Starfire Systems, Inc. & U.S. Army Research Laboratory
Principal Investigator: Prof. Rao Tummala
Project: Functionally Integrated Reactive Surface Technologies Project 1
The Army Research Labs, through Starfire Systems, awarded a five-year contract with a $2.1 million ceiling to develop embedded sensing/electronics in smart textiles for an integrated intelligent uniform for the soldier or first responder. This co-operative research agreement is in partnership with Starfire Systems, Syracuse University and Albany Nanotech (University at Albany).
Purpose: To demonstrate an ultra-microminiaturized hybrid circuit with System-On-Package technology that will enable the integration and combination of multiple sensors, micro-controllers, and wireless communication into a robust “patch” circuit, the size of a name tag on a soldier uniform. This circuit can control the active fabric, communicate via wireless within the uniform, or with the command infrastructure to maintain the human performance of the soldier experiencing a chemical-biological warfare (CBW) attack.

Matsushita Electronics (Panasonic)
Principal Investigator: Prof. Madhavan Swaminathan
Project: PanSwitch-Customized Simultaneous Switching Noise Simulator for Co-simulation of Signal Interconnects and Power Distribution
Purpose: Mixed Signal Packages have split ground planes for achieving high levels of isolation. Modeling such structures can be difficult using commercial full wave solvers. The focus of this research is to develop an EDA tool that can model complex packages containing split planes in the presence of signal interconnects that are at least 100X faster than commercial electromagnetic solvers.

IBM Corporation
Principal Investigator: Prof. David Keezer
Project: High Speed, Multiplexed Test Method Development and Demonstration
Purpose: This project develops multiplexing and sampling circuits to combine parallel test channels of automated test equipment (ATE), thereby enabling testing devices at higher speeds. In the first two years of the project, the ATE limit of 1 Gbps has been extended to 5 Gbps. This latest award (third-year) provides for extending the functionality of the circuits (including testing of source-synchronous signals) and for improving performance.

University of Michigan
Principal Investigator: Prof. Farrokh Ayazi
Project: Environment-Resistant Micromachined Inertial Gyroscopes
Purpose: This project investigates the performance and power limits of integrated micro-vibratory gyroscopes at the micromechanical sensor, electronics, and package level. The goal is to implement the next generation of integrated MEMS gyroscopes with accuracy and stability levels better than 0.1 degree/hour and less than 10 milliwatts of power consumption. Packaging plays an important role in maintaining the necessary high quality factors of the mechanical sensor while providing thermal, shock, and vibration isolation.

Semiconductor Research Corporation
Principal Investigator: Prof. Madhavan Swaminathan
Project: Modeling and Simulation Methods for Signal and Power Delivery Networks in System in Package Technologies
Purpose: The focus is the development of an EDA environment that model the electrical behavior of complex System in Package environments that contain inhomogeneous media.

National Science Foundation
Principal Investigator: Prof. Leyla Conrad
Project: STEP-UP: Summer Teacher Experience in Packaging, Utilizing Physics
Purpose: The STEP-UP program provides a comprehensive high school teacher research experience at the Microelectronics Packaging Research Center (PRC), an NSF Engineering Research Center (ERC), in collaboration with the School of Physics at the Georgia Institute of Technology. The objective of this program is to train high school teachers in both modern physics concepts and their applications to engineering and their relevance to today’s technology. It provides them with a research experience at the PRC’s engineering laboratories that they can take back to their classrooms. This goal is achieved in three steps: (1) a two-week course on modern physics, with a laboratory component that enables teachers to fully take advantage of their subsequent research experience; (2) a one week module course on applications of modern physics concepts to microelectronics packaging; and (3) a five-week summer research experience. In addition, four workshops are held during their stay at Georgia Tech to develop lesson plans and classroom material encompassing their research experience.