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Georgia
Institute of Technology |
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| e-newsletter Vol. 1, Issue 2 – March 2004 |
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PRC Defines and Distinguishes SOP from 3D, SIP, MCM and SOC
The System-on-Package (SOP) being pursued by the PRC is different from and offers advantages over MCM, 3D packaging and SIP. The 3D packaging is a general concept of interconnecting discrete layers after fabrication, electrical test and repair, if necessary, to yield. The 3D, in the past, is also used to describe the stacking of similar chips such as DRAMS. MCMs, on the other hand, simply interconnect ICs or components horizontally or in 2D. The SIP goes beyond and stacks similar or dissimilar ICs and it may even embed both actives and passives. But the passives in SIP are typically currently-available, discrete, thick and bulky components. The SIP stacking can be either die stacking or package stacking. The SOP goes one step further in the ultimate 3D integration of components in thin-film form at microscale in the short term, and nanoscale in the long term. For example, decoupling capacitors can be several millimeter-thick discrete ceramic capacitors made of multilayer thick film technologies, or they can be one layer of ultra-thin film technologies that are about a micron or less in thickness. Embedding of millimeter-thick, currently-available, discrete, multilayer, thick-film capacitors is typically done in SIP, whereas ultra-thin film is done in SOP. But SOP is more than capacitors; it is filters and antennas. It is also the embedding of thin-film optical components such as detectors, lasers, waveguides, etc.
NSF Recognizes Two National Contributions of PRC in the U.S.
The National Science Foundation recently cited two of the PRC's contributions as National contributions among all its ERCs in the US:
PRC Demonstrates
SOP Concept by the First Miniaturized Digital-Optical-RF Convergent System
"The PRC's SOP electronic package will usher in a new paradigm for communication
and computer technologies that will integrate voice, video, and data on a single,
miniature module [at 10 Mbps wireless over 10 Gbps links]. The current standard
is 10 Mbps per second. These results demonstrate the validity of the Center's
System-on-a-Package concept for emerging convergent systems. These advances
in digital, RF, and optoelectronic integration using SOP technology were made
in collaboration with the PRC's industrial partners. Semiconductor Companies
can extend the life of silicon technology by realizing improved cost-performance
benefits from moving some of the critical functions originally designed for
on-chip into the SOP platform [with the PRC's focus on] IC-package co-design."
“The high risk
of this work is the focus on systems and the need to push integration frontiers
in an academic research environment. This approach to integration is leading
industry in new directions and producing engineering graduates experienced in
interdisciplinary approaches to systems integration consistent with industry
needs and practices. The advances were made by electrical, chemical, and mechanical
engineers in collaboration with materials scientists and physicists.”
State-Industry-University
Partnership Builds Leading-Edge Plating Facility
"A primary goal of the Engineering Research Centers Program is to develop
an interdisciplinary culture in academe where students can gain the full range
of the engineering experience, from fundamental inquiry to design, to build.
This facility provides a national resource for both research and education not
only to Center-affiliated faculty and students but also to users from industry
and other universities."
This Month’s Research Focus: Wafer Level Packaging from Micro to Nanoscale
Wafer Level Packaging research at the PRC focuses on novel interconnect technologies to meet electrical, mechanical, cost and performance requirements consistent with the ITRS roadmap for 5-20 Ghz digital and up to 60 Ghz RF systems. The interconnect technologies include both polymer-based and metal-based, spanning from 100 micron to 20 micron bump pitch, the latter with Nanoscale interconnections. The initial test bed focuses on demonstrating 100 μm pitch with lead-free solder and underfill assembly process to meet >1000-thermal-cycle reliability and with <20mΩ DC resistance, <50pH inductance and <10fF capacitance. In addition, a long-term strategic testbed with a 20 μm pitch area array assembly based on nanoscale interconnections is being pursued. The projects thus include polymer-based research and metal-based research as follows:
| Polymer-based Interconnects | Metal-based Interconnects |
|
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PRC
Continues to Push Underfill and Conductive Polymers for Assembly
The PRC’s research in polymer-based interconnection materials includes
the materials and process such as nanosilica composite no-flow and wafer level
underfill, high current density anisotropic conductive adhesives (ACAs), and
high corrosion resistant isotropic conductive adhesives (ICAs). A novel B-stageable
wafer level underfill, and its curing kinetics have been developed. The underfill
has shown desirable mechanical properties and minimum wafer warpage after it
is B-staged. Good wetting behaviors of the eutectic SnPb solder and lead-free
solder have been observed with the presence of the wafer level underfill. Nanosilica
with chemical surface treatment has been incorporated into the underfill. The
material properties of the underfill are significantly enhanced due to the nanosilica
incorporation. The CTE of the nanocomposite underfill is reduced to 46 ppm/°C,
and modulus is increased to 4.5 GPa with 40 wt% loading of nanosilica, with
much better optical transparency compared with the conventional underfill. Electrical
conductive adhesives with high corrosion resistance have been developed through
incorporation of sacrificial-anode alloy. Stable contact resistance has been
achieved on different surface finishes including lead-free surfaces up to 500
hours under 85°C/85RH conditions. Current research is focused on the application
of self-assembled monolayer (SAM) to increase the current-carrying capability
of ACAs. For more information, please contact Prof. C. P. Wong (cp.wong@mse.gatech.edu).
PRC
Targets 100 µm Pitch Package and Assembly with Lead-free Solders and Underfill
for Demonstration in 2004
The PRC proposes to integrate its research in new Core/board, next gen microvia
package and assembly technology into a testbed to demonstrate 100 µm pitch
with lead-free solder and underfill assembly process to meet >1000-thermal-cycle
reliability and with <20mΩ DC resistance, <50pH inductance and <10fF
capacitance. The short term focus is on Sn95.5-Ag3.8%-Cu0.7 lead-free solder
interconnect material. The assembly research covers interconnect bumping processes,
assembly processes with underfill materials as well as inter-metallic formation
and its effect on electrical and mechanical properties.
In addition, a long term strategic testbed with a 20 µm pitch area array assembly based on nanoscale interconnections is being pursued.
PRC
Explores Alternatives to Solders, Starts Nanoscale Interconnection Research
for Unlimited I/Os
Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical
reliability requirements at very fine pitches on the order of 50 microns or
less. To achieve the requirements of very fine pitch with conventional interconnects,
we have to accept a trade-off in electrical and mechanical performance and possibly
cost. Current low stress interconnects for improved mechanical performance at
fine pitch use compliant metallic structures with complicated processing steps
and compromised electrical performance (high inductance and resistance). These
design constraints are imposed by the inherent high stiffness of metals. Novel
polymers, with stiffness 100-200 times lower than that of metals, are ideal
materials for low-stress interconnects. These polymers can be electroless coated
to thickness greater than the skin depth for high-speed signal propagation,
without any effect on the electrical parasitics. The PRC recently demonstrated
copper-coated polyimide structures (CTE of 3 ppm/C) with a pitch of 20 microns.
These novel low stress nano-structured interconnects can be further downscaled
to any pitch, enabling the dream of realizing unlimited I/Os.
Reworkable IC assembly, which essentially is being able to replace bad chips with good ones, is an important aspect of low-cost wafer-level packaging. Our approach addresses reworkability with nano-dimensional bonding interfaces leading to nano interconnections with the least parasitics. Two novel low cost material synthesis routes were demonstrated to yield the reworkable liquid interfaces for IC-substrate bonding. 20 micron pitch assembly was demonstrated by combining the metal-coated polymer interconects with low-stress with thin film reworkable interfaces.
PRC Begins Baseline Process for its Mixed-Signal Systems Research
Requests Industry's
Input and Designs for Process Technology Demonstration
The PRC has begun the most aggressive SOP module development to date
using advances in BCB and other dielectrics processing. The new design and process
initially uses BCB as a digital, RF and optical material for mixed-signal systems.
The digital block uses four layers of BCB as the insulating dielectric, with
each dielectric layer having a thickness of 9µm and six metallization
layers on a single-sided, high modulus substrate. The metallization is accomplished
through a novel wet seeding process of BCB, developed by the PRC, followed by
full electroless plating of the studs and traces. The resultant geometry is
a stacked via structure that integrates resistors, capacitors and inductors
in a multilayer high performance mixed-signal SOP package. The stacked via geometry
is accomplished in the absence of any chemical-mechanical polishing, thereby
resulting in the highest wiring density per unit area, at the low cost.
Currently, the PRC is soliciting industry designs or inputs for technology demonstration of this process. The design guidelines can be obtained via the PRC web site. For additional information, please contact Venky Sundaram at vsunda@ee.gatech.edu or George White at georgew@ee.gatech.edu.
PRC’s Recent Publications in Assembly Research
A. Underfill
and polymer based interconnects
Z. Zhang, and C.P. Wong, "Characterization of the Curing Properties of No-Flow
Underfill and B-Stage Feasibility Study for Wafer Level Application", Proceedings
of the 53rd Electronic Components and Technology Conference, pp. 971-977, New
Orleans, LA, (2003).
R. Doraiswami, S. Sankararaman, W. Kim, J. Li, Z. Zhang, P. Gupta, K. Nakanishi,
M. Borkar, R. Madhavan, V. Govind, S. Choi, A.O. Aggarwal, Y. Sun, L. Fan, V.
Sundaram, M. Swaminathan, C.P. Wong, R.R. Tummala, "Advances in Fine Pitch Lead
Free Assembly Process", Proceedings of the 53rd Electronic Components and Technology
Conference, pp. 834-839, New Orleans, LA, (2003).
Z. Zhang, and C.P. Wong, "Recent Advances in Wafer Level Packaging", Proceedings
of he 3rd Annual IEEE Photonic Devices and Systems Packaging Symposium and Photonics
Materials Reliability Symposium, p. 88-93, San Francisco, CA, August 10-14,
2003.
Z. Zhang, Y. Sun, L. Fan, R. Doraiswami, C.P. Wong, "Development of Wafer Level
Underfill Material and Process", Proceedings of 5th Electronic Packaging Technology
Conference, Singapore, p. 194-198, Dec 2003.
W. Kim, R. Madhavan, J. Mao, J. Choi, S. Choi, D. Ravi, V. Sundaram, P. Gupta,
Z. Zhang, G. Lo, M. Swaminathan, R. Tummala, S. Sitaraman, C.P. Wong, M. Iyer,
M. Rotaru, and A. Tay, "Electrical Design of Wafer Level Package on Board for
Gigabit Data Transmission", Proceedings of 5th Electronic Packaging Technology
Conference, Singapore, p. 150-159, Dec 2003.
Z. Zhang, E. Beatty, C.P. Wong, "Study on the Curing Process and the Gelation
of Epoxy/Anhydride System for No-Flow Underfill for Flip-Chip Applications",
Macromolecular Materials and Engineering, Vol. 288, pp. 365-371, (2003).
Haiying Li; Kyoung-Sik Moon; Wong, C.P, "Effect of Sacrificial Anodic Fillers
on Contact Resistance Stability of Electrically Conductive Adhesives onto Lead-Free
Alloy Surfaces", IEEE Electronic Components and Technology Conference, 2003.
Proceedings. 53rd , May 27-30, Page(s): 1373 -1377 (2003).
K. Moon, C. Rockett, C. Kretz and W. F. Burgoyne and C.P. Wong, "Improvement
of Adhesion and Electrical Properties of Reworkable Thermoplastic Conductive
Adhesives", Journal of Adhesion Science & Technology, 17(13), 1785 (2003).
B.
Nano materials and metal -based interconnects
Shubhra Bansal, P. Markondeya Raj, Swapan Bhattacharya, Michael J. Lance, Rao
Tummala, "In-situ stress and warpage measurement to investigate reliability
of flip-chip-on-board assembly without underfill", Electronic Components
and Technology Conference, pp. 148-155, ECTC May 27-30, 2003, New Orleans, Louisiana,
USA.
Ankur O. Aggarwal, I R Abothu , P. Markondeya Raj, M. D. Sacks, Rao R. Tummala,
"Novel Low-Cost Sol-Gel Derived Nano-structured and Repairable Interconnects",
Proceedings, International Microelectronics and Packaging Society, 2003, pp.
943-949, Boston, MA, November, 2003.
Ankur O. Aggarwal, I R Abothu , P. Markondeya Raj, M. D. Sacks, Rao R. Tummala,
" Sol-Gel Derived and Repairable Interconnects, Proceedings - Electronic
Packaging and Packaging Technology Conference, December 10-12, 2003, Singapore,
pp. 385-389.
Nitesh Kumbhat, P. Markondeya Raj, S. Bansal, R. Doraiswami, Swapan Bhattacharya,
Rao Tummala, Susan Hayes, Steve Atmur, "New package/board materials technology
for next generation convergent electronic systems", Proceedings - Electronic
Packaging and Packaging Technology Conference, December 10-12, 2003, Singapore,
pp. 331-335.
Shubhra Bansal, P. Markondeya Raj, Swapan Bhattacharya, Michael J. Lance, Rao
Tummala, "In-situ stress and warpage measurement to investigate reliability
of flip-chip-on-board assembly without underfill", Electronic Components
and Technology Conference, ECTC May 27-30, 2003, New Orleans, Louisiana, USA.
PRC to Offer Summer Tutorials on SOP and Next Generation Advanced Packaging Technologies
The PRC annually offers a comprehensive set of short courses on SOP and next-generation microsystems packaging technologies. This year’s course series consists of individual modules taught by highly respected Georgia Tech PRC faculty. The individual modules are based on the PRC’s System-on-Package vision which integrates not only digital but also analog, RF, optical and MEMS functions into one ultra-compact and low-cost mixed signal package system to serve the needs of convergent telecom, consumer and computer systems of the next decade. This year’s short course series will focus on three areas:
The titles and schedules of the individual modules to be offered are provided in the table below. More information about each course or instructor can be obtained by clicking on the course title.
| Date | Module Title | Instructor | Course Fees* | |
On
or Before 5/10 |
After
5/10 |
|||
| May 24 8am-12pm |
Introduction to Nanoscale Packaging and Systems | Tummala & Wang | $295 |
$350 |
| May 24 1pm-5pm |
MEMS and NEMS Packaging | Ayazi | $295 |
$350 |
| May 25 8am-5pm |
RF/Wireless Packaging: Fundamentals, Principles, and Current Challenges | Tentzeris & Laskar | $495 |
$550 |
| May 26 8am-12pm |
Optoelectronics Integration | Chang & Adibi | $295 |
$350 |
| May 26 1pm-5pm |
Wafer Level Packaging: Materials, Process, and Reliability | Wong | $295 |
$350 |
| May 27-28 8am-5pm |
Low Cost Flip Chip Processing and Analysis with Hands-On Applications | Baldwin, Houston, & Lewis | $995 |
$1,100 |
Full
week registration fee: $2,250 (on or before 5/10) and $2,500 (after 5/10)
* PRC member company engineers receive a 20% discount.
For further information, please visit: http://www.prc.gatech.edu/academics/contEd/2004/index.htm
Member Company Recruiting of PRC Students
Electronics companies who join the PRC in collaborative efforts have exceptional advantages in recruiting the very best PRC students. (See, “PRC Industry Partnership and Membership Structure” in this issue). Students who have completed the PRC’s educational programs have the maximum amount of training and education, thus preparing them for full-time work in the electronics industry. Since the industry plays a vital role in shaping the curricula and in mentoring the PRC’s students, the PRC's programs prepare students to "hit the ground running" when they arrive to start their careers in design, research, development, manufacturing or business development. The fundamental education is broad and provides an excellent understanding of fundamental sciences such as physics and chemistry and yet specialize in the engineering and packaging areas most needed by the electronics industry. Since the curricula are highly cross-disciplinary, a mechanical engineering major from the PRC will also have experience in electrical, materials and chemical engineering. He/she will also understand manufacturing and assembly from design to build to operate (DBO). Additionally, through the PRC’s Practice Oriented Masters Program in SOP, students are educated in business, communication skills, leadership and management.
The PRC provides resume posting services for students at all degree levels. Each semester, members are given the opportunity to preview resumes at the PRC member website where resumes are posted for a period of approximately 30 days prior to being moved to the PRC's public website. Members may also utilize the PRC's periodic Industrial Advisory Board (IAB) meetings to meet one-on-one with selected students for employment interviews.
For further information on recruiting, please contact Dr. Leyla Conrad, PRC Associate Director for Education, at (404) 894-385-0439, or via e-mail to leyla.conrad@ee.gatech.edu.
Member partners interested in viewing students’ resumes can click on "Member Login Page" found under the “Industry Partnership” menu heading on the PRC home page at: www.prc.gatech.edu.
PRC Proposes the First International Workshop on 3S (SOP, SIP, SOC) Technologies
October 21 &
22, 2004 • Georgia Tech, Atlanta, GA, USA
The SOP paradigm
changes the current chip-centric SOC methodology to a cheaper, faster-to-market
IC-package-system co-design flow. The advantages of the SOP paradigm over SOC
appear overwhelming due to SOP’s design simplicity, lower cost and higher
system function integration, electrical performance, without the intellectual
property issues that dominate SOC. The SOP is also different from and offers
advantages over 3D packaging and SIP. The 3D packaging is typically stacking
of similar, or dissimilar, chips such as DRAMS. The SIP goes beyond to embed
both actives and passives but the passives are discrete, thick and bulky components.
The SOP goes one step further in the ultimate 3D integration of components in
thin film form at microscale, in the short term, and nanoscale in the long term.
The SOP focuses on integrating both single function as well as heterogeneous
system functions, optimizing ICs for transistors and package for integration
of digital, RF, optical, sensor and others. It accomplishes this by both build-up
SOP, similar to ICs and stacked SOP, similar to parallel board fabrication.
This workshop reviews the latest R & D and manufacturing status of each of the 3 electronic technologies around the world. It will also attempt to compare and contrast SOC, 3D stacking, SIP, SOP and MCM.
Proposed sessions:
SOP, SIP, SOC and 3D Technologies
PRC Revises its Industry Partnership and Membership Structure
A critical part of the PRC’s vision is its partnership with global industry. This partnership is for joint system-on-package (SOP) research and development leading to technology transfer and for educating and transferring a new breed of engineers to industry for scale up and commercialization of the new SOP technologies. To accomplish this partnership, PRC has recently reorganized its membership structure to include a wider variety of strategic collaboration partnership mechanisms to benefit industry, including:
Other modes of interaction can also be effective with industry and governmental organizations for specific, objective-oriented collaborations in both short term and long term.
New SOP Advanced Plating System
The PRC, in partnership with ATOTECH USA—a plating equipment and chemistry provider—has installed and begun process qualifications of the new vertical electroless and electrolytic plating system. The core of this partnership is the development of equipment, chemistries and processes needed to realize ultra high density structures for the Center’s SOP test beds leading ultimately to technology transfer to member companies.
The 60-foot system contains 57 process steps for pretreatment and plating processes and will be used for both panel and pattern plating. Flexible in its operational configuration, the process tanks have ultrasonics, heating, cooling, mechanical rack agitation, filtered recirculation and bubbling. The system can be operated with all, none, or any combination of these features running. Initial capabilities of the system include: electroless copper and nickel, immersion gold, electrolytic copper, tin-lead, with expansion to include silver plating. The system is a modular concept, permitting baths to be swapped out, as chemistry and process needs dictate.
PRC Student Awarded Best Paper at IMAPS-Boston
The Best Paper award went to the Packaging Research Center’s very own Ankur Aggarwal, graduate student in the School of Materials Science and Engineering. The winning paper, "Novel Low-Cost Sol-Gel Derived Nano-structured and Repairable Interconnects," was presented at the International Microelectronics and Packaging Society, November 2003 in Boston. Other contributors to the paper’s winning success were Isaac Robin Abothu, Pulugurtha Markondeya Raj, M. D. Sacks and Professor Rao R. Tummala.
PRC Cooperative Education Student Receives Student of the Year Award
After
spending summer and fall of 2003 at the PRC as a co-op student, Suman Rasi Subramaniam
returned to his home institution, the New Jersey Institute of Technology (NJIT).
A few months later, he receieved great news: he had been nominated for and would
be awarded NJIT’s Co-op Student of the Year award in recognition of his
outstanding performance as a cooperative education student at the Georgia Institute
of Technology’s Packaging Research Center.
On March 3, Suman was publicly honored at the Division of Career Development Services Awards Ceremony at NJIT. A certificate and a great sense of accomplishment also accompanied the recognition.
Congratulations, Suman!
Georgia
Institute of Technology Packaging Research Center
- An NSF Engineering Research Center -
Leading the SOP & Nano Packaging Paradigms in Partnership with Global
Industry
For further info, please visit: http://www.prc.gatech.edu
PH: 404-894-9097, FAX: 404-894-3842 • 813 Ferst St., MaRC Bldg. 351 • Atlanta, GA 30332-0560
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