DIRECTOR'S CORNER
INDUSTRY-PRC CONSORTIA: MSDT EMAP
RESEARCH ADVANCES
PARTNERSHIPS & CONTRACTS
AWARDS & RECOGNITION
PATENTS & INVENTIONS
PUBLICATIONS
PRC SUMMER PICNIC

3S WORKSHOP
PRC NEW TEAM MEMBERS
TEAM MEMBER HIGHLIGHT
CONFERENCES & WORKSHOPS
EDUCATION PROGRAMS
FACULTY HIGHLIGHT
VISITING ENGINEERS
PRC CONTACT INFORMATION

Director’s Corner

PRC has begun the transition from NSF-centric to Global Industry-centric. Over the last 11 years, the PRC has been a National NSF Center focusing on an integrated approach to Research, Education and Industry Collaboration in the SOP technology paradigm. During this period, it had pioneered SOP technology, developed extensive expertise, facilities and collaborated with more than 150 companies around the globe, transferring parts of SOP technologies to them. It has also made Packaging as an academic subject for the first time, with courses, curricula and textbooks, and graduating around 575 students.

The PRC transition is taking place in research with newer emerging technologies such as embedded actives and passives, nano-bio-info technologies, and in research staff to address these newer technologies and to work with industry more effectively.

The PRC is now very Industry-centric and Global. It works with global industry in exploring newer technologies at project level, and in addition, it is setting up large thematic, program level consortia on a variety of topics such as Design Tools, Embedded Actives and Passives, Thermal Interface Materials, Mixed Signal Test, Nano Materials and Packaging, etc. Given its breadth of know-how from Design to Prototype, on one hand, and complete cleanroom facilities on the other hand, it is also embarking on large company contracts to demonstrate the next generation of SOP-based modules.

To make this transition, it has set up a new management team with Prof. Madhavan Swaminathan as Deputy Director, Dr. Mahadevan Iyer as Research Director, Dean Sutter as Finance and Infrastructure Director and three Assistant Research Directors: Dr. Raj Pulugurtha, Dr. Chong Yoon and Venky Sundaram. In addition, it continues with Research Faculty Directors, Prof. Swaminathan for SOP Design, Prof. John Papapolymerou for RF SOP, Prof. Gee-Kung Chang for Opto SOP, Prof. C. P. Wong for Wafer Level Packaging and Assembly.

The PRC is thus reinventing itself and beginning to grow in newer research areas and in new ways to collaborate with the global industry.

Prof. Rao R. Tummala
Endowed Chair Professor
Director of PRC, Georgia Tech

Mixed Signal Design Tools (MSDT) Consortium Focuses on Next Generation EDA for Integrated Microsystems
Launch Planned for October 2006 | Web Info | Area Hotels

GT-PRC held a pre-launch meeting on June 21, 2006 with the companies joining the MSDT consortium. The focus of this consortium is the development of next generation design tools that enable the deployment of SiP (System in Package) and SoP (System on Package) technologies. These tools will interface with commercially available package layout tools and are expected to seamlessly fit into an existing design flow. Along with providing analysis capability, they can also be used to influence designs in an iterative manner. Hence, the goal of the consortium is to develop EDA tools that enable both design and verification. The following topics will be covered in the consortia:

• Electromagnetic Modeling
• Circuit Simulation Methods
• Design Automation
• System Analysis and Testbeds
• Behavioral Modeling

Companies interested in joining the consortium are encouraged to contact Prof. Madhavan Swaminathan (madhavan.swaminathan@ece.gatech.edu), Dr. Mahadevan Iyer (mahadevan.iyer@ece.gatech.edu), or Dr. Ege Engin (engin@gatech.edu).

Embedded Actives and Passives (EMAP) Consortium Development
Launch Planned for October 2006 | Web Info | Area Hotels

The PRC initiated its Embedded Actives and Passives (EMAP) consortium on February 8 th, 2006 and hosted its first workshop on June 20 th, 2006 , followed by a pre-launch meeting with 9 consortium member companies around the world. During the pre-launch, member companies selected 11 key projects as a two-year, Phase I research collaboration. The PRC has learned that other major companies from system and component level, as well as supply chain level, have expressed interest in joining the Phase I program scheduled to launch in October 2006. For further information, please visit these web URLs:

• PRC Consortia Programs: www.prc.gatech.edu/consortia
• Mixed Signal Design Tools: www.prc.gatech.edu/events/2005/digital
• Embedded Actives & Passives: www.prc.gatech.edu/pr/emap06pr.htm
• Thermal Interface Materials: www.prc.gatech.edu/events/tim
• Electrical Test and Fault Tolerance: www.prc.gatech.edu/events/etft

You may also contact Dr. Mahadevan Iyer (mahadevan.iyer@ece.gatech.edu) or Dr. Chong Yoon (cyoon@ece.gatech.edu) for further information.

	The PRC’s consortia development team recently held collaborative workshops with industry to discuss problems and solutions in areas such as Mixed Signal Design Tools, and Embedded Actives & Passives. The next industry-academia workshops will be held on September 27, 2006 on Thermal Interface Materials, and on November 7, 2006 focusing on Electrical Test and Fault Tolerance for System-On-Package and System-In-Package (ETFT). For further information on "ETFT" visit www.prc.gatech.edu/events/etft For further information on all PRC Consortia Development Workshops, visit: www.prc.gatech.edu/consortia

Research Advances & Innovations

Embedded RF Capacitors in Organic Substrates with Near Zero TCC
In our research to achieve Temperature Coefficient of Capacitance ( TCC ) near zero, for the first time the PRC has developed new fillers with core-shell structure with separate ceramic phases. These fillers would be used in epoxy matrix in our polymer composite capacitor research and demonstration of the concept is underway with U.S. patent pending. This research also focuses on achieving high dielectric constant as well high-Q capacitors with manufacturable low-cost technology. This was also presented at 2006 ECTC (Electronic Components and Technology Conference) conference at San Diego , CA , May 30- June 2, 2006 . Contacts: Dr. Isaac Robin Abothu (robin@ece.gatech.edu) or Dr. Baik-Woo Lee (baikwoo@ece.gatech.edu)

Prototype Demonstration of New 3D SIP Chip Stacking by Wire-On-Bump (WOB) and Bump-On-Flex (BOF)
Two new 3D chip stacking technologies, WOB (Wire-on-Bump) and BOF (Bump-on-Flex), were proposed and demonstrated with their prototypes, which can address: (1) stacking of unlimited number of memory ICs without engineering limits such as with wire-bonding, (2) short vertical interconnection for better electrical performance and (3) lower cost. The WOB technology is about vertical interconnection of peripheral bumps on stacked chips by conductive wires. The BOF technology uses a flex-circuit to connect the peripheral bumps, instead of the wire in the WOB. The flex-circuit includes metal lines and bumps-on-pads on flexible organic materials as well as embedded thin film components if necessary. This was also presented at 2006 ECTC (Electronic Components and Technology Conference) conference at San Diego , CA , May 30 ~ June 2, 2006 . Contacts: Dr. Chong Yoon (cyoon@ece.gatech.edu), Dr. Baik-Woo Lee (baikwoo@ece.gatech.edu) or Prof. Rao Tummala (rao.tummala@ee.gatech.edu).

Nanopower Generators
PRC’s Prof. Z. L. Wang demonstrated an innovative nanotechnology for converting mechanical energy (such as body movement, muscle stretching), vibration energy (such as acoustic/ultrasonic wave), and hydraulic energy (such as body fluid and blood flow) into electric energy that will be used to power nanodevices without using battery. It has a huge impact to miniaturizing the size of the integrated nanosystems by reducing the size of the power generator and improving its efficiency and power density. The device converts nanoscale mechanical energy into electrical energy by means of piezoelectric zinc oxide nanowire (NW) arrays. To demonstrate nanogeneration of energy, the aligned NWs are deflected with a conductive atomic force microscope tip in contact mode. The coupling of piezoelectric and semiconducting properties in zinc oxide creates a strain field and charge separation across the NW as a result of its bending. The rectifying characteristic of the Schottky barrier formed between the metal tip and the NW leads to electrical current generation. The efficiency of the NW-based piezoelectric power generator is estimated to be 17 to 30%. This approach has the potential of converting mechanical, vibrational, and/or hydraulic energy into electricity for powering nanodevices. Contact: Prof. Z. L. Wang (zhong.wang@mse.gatech.edu)

Optoelectronics Scalability and Manufacturability in PCB Environment
A major challenge in the integration of optical waveguides on a high density electrical interconnect printed circuit board (PCB) is the rough and irregular surface of the substrate. A planar and smooth organic substrate having a few nanometers roughness surface has been developed at the PRC, enabling the fabrication of high quality waveguides and waveguide based devices on the high density interconnect PCB. Scalability and manufacturability due to process induced defects is a concern for optical interconnect PCBs. Contamination and dust particles may be introduced during coating, baking, exposure, developing, and curing. Mechanical scratches and damage are induced by mask contact and handling. We have developed a CapClad process technology in which the waveguide core is protected during the fabrication process so that the defects are greatly reduced and the manufacturing yield should be improved. Experiments have shown that this technology has over 20% improvement of propagation loss for a waveguide compared with the conventional waveguide made in a PCB compatible environment. This innovation will improve yield for embedded optical interconnects in PCBs without the need for expensive clean rooms. Contacts: Dr. Fuhan Liu (fliu@ece.gatech.edu) or Prof. G. K. Chang (gk.chang@ece.gatech.edu)

PRC Demonstrates Novel Thin Film RC Integration
In the first generation of SOP, PRC developed compatible resistor and capacitor technologies using photo definable ceramic polymer nanocomposite capacitors and screen-printed polymer thick film resistors that were patterned using a lift-off process. Now working on the second-generation SOP, PRC extended this to ultra thin film technologies. Recently, PRC integrated thin film hydrothermal capacitors (200 nm, 500 nF/cm 2, BDV 10 V) with thin film resistors of CrSiO (1000 ohms/square) for very high value capacitances (60 nF) and resistances (40,000 ohms). Low temperature thin film synthesis routes, photo patterning and wet etching were used for the RC integration to make them compatible with each other and with low cost substrate technologies. Compatible resistors and capacitor technologies on the same layer is very critical for the total system miniaturization. PRC will now extend this technology to mixed signal and sensing applications. Contact: Swapan Bhattacharya (swapan@ece.gatech.edu)

High-Frequency Dielectric Constant and Loss Tangent Characterization of Thin High-K Dielectrics
Thin dielectrics with a high dielectric constant are very attractive for improving the decoupling performance of digital and mixed-signal systems. Accurate estimation of the dielectric constant and the loss tangent is important to calculate the impedance profile or the cavity resonances. Extracting the electrical properties of thin and high-K dielectrics is difficult using conventional methods such as microstrip or ring resonators with gaps, as the coupling through the gap becomes very small for an accurate measurement. We have developed a method to extract the frequency-dependent dielectric constant and loss tangent of such materials using rectangular power/ground planes. We have also developed a rapid plane solver for fast and automated extraction of material properties from such measurements. We applied this rapid solver method to characterize a thin high-K material, but we believe it can be used for thick or low-K materials as well. Contact: Dr. Ege Engin (engin@ece.gatech.edu)

Compact Electromagnetic Bandgap Structures for Power Plane Isolation
Electromagnetic bandgap (EBG) structures have been successfully applied for isolating sensitive analog circuits from digital switching noise in mixed-signal designs. EBG structures have to be small, since the total package or board area is a major concern especially in portable devices. PRC has recently demonstrated how to scale such EBG structures to obtain compact sizes suitable for integration in a package using materials with high dielectric constants. This approach allows the integration of EBGs in packages covering sufficiently low frequencies commonly used in wireless applications. Contact: Dr. Ege Engin (engin@ece.gatech.edu)

Ultra-fine Pitch Interconnects Made by Carbon Nanotubes for Flip-chip Technology
Carbon nanotube ( CNT ) is one of most promising candidates to replace the traditional metal solders or wires for the interconnection between IC chip and substrates, due to its superior electrical, mechanical and thermal properties. However, the carbon nanotube growth needs the high temperature process which makes it impossible to be adopted into the microelectronics assembly. GT-PRC developed a novel growth method of CNT by Chemical Vapor Deposition ( CVD ). With this method, the patterned CNT arrays can be easily fabricated at large scale and transferred to the silicon chip or other substrate under the reflow temperature. The whole process is compatible to the IC fabrication and assembly line. The as-formed CNT arrays on the chip have excellent thermal and electrical conductivity, good adhesion and negligible thermal expansion. With the different design of the pattern, an ultra-fine pitch-size and high density interconnects can be achieved. These results show that CNT arrays can provide a superior solution for next-generation electronic packaging. Contacts: Prof. C.P. Wong (cp.wong@mse.gatech.edu) or Jack Moon (ks.moon@mse.gatech.edu)

Electrochemical Etching Based Heat Exchangers
Recent research in the thermal management group has been concerned with developing low-cost electrochemical copper etching methods for forming micro/meso heat exchangers for a variety of electronics cooling applications. Copper is a convenient material to work with due to its high thermal conductivity. By controlling the mass transfer processes and voltage-current regimes in electrochemical etching, the anisotropy and rate of etch should be more controllable than in chemical wet etching. In addition, the etching solution is not "used up" as in traditional ferric chloride or ammonium persulphate etchants, therefore reducing cost and environmental impact. Fractal or dendritic flow paths are being investigated to minimize maldistribution of coolant and to optimize heat transfer. Contact: David Gerlach (dg179@mail.gatech.edu)

Partnerships and Contracts

Contract Partner: Radiance Technologies, Inc.
Funding Type: Missile Defense Agency Small Business Innovation Research Program (SBIR), Phase II
Project Title: Continuous Hypergolic Monitor Network for Shipboard Application
Research Area: SOP based MEMS chemical sensors
Purpose: To complete an integrated sensor system to detect hypergolic fuel leaks aboard naval vessels. The system will monitor continuously or intermittently at numerous locations, and be capable of detecting multiple hypergolic materials. The sensing will rely on a solid polymer electrolyte based MEMS electrochemical sensor, fabricated on organic substrate. Nano material (Carbon Nano Tube or other novel material) will be investigated and applied to improve the sensitivity. These MEMS devices will be integrated both in the organic and Si platforms to demonstrate System-On-Package based nano-chemical sensor.

Contract Partner: National Science Foundation
Faculty Member: Prof. Suresh Sitaraman
Project: Fixtureless Stress-Engineered Test Methods for the Measurement of Interfacial Fracture Toughness for Micro- and Nano-Scale Thin-Film Interfaces
Research Area: Reliability and Material Characterization
Purpose: Micro- and nano-scale thin films are being increasingly used in a wide range of applications, and the experimental characterization of interfacial properties of such thin films is challenging, yet necessary for design against interfacial delamination. This proposal aims to develop an innovative fixture-less superlayer based decohesion test with a sandwiched etchable release layer to measure the interfacial fracture toughness of a thin film deposited on a substrate. Two versions of the proposed test will be developed: in the single-substrate version, the release layer will have a uniform width, while in the single-strip version, the release layer will have a varying width. Thin-films with thickness ranging from 50 nm to few microns will be studied.

Renewed Industry Contracts
We're pleased to report that the following companies recently renewed contracts for continued research collaborations with the PRC. We publicly thank them for the opportunity to support their research interests.

ALTERA • ATOTECH • INTEL • NGK/NTK • PANASONIC • ROHM & HAAS • TEXAS INSTRUMENTS

Awards & Recognitions

Outstanding Faculty Leadership Award
An award was presented to Professor Suresh Sitaraman on April 12, 2006 for "Outstanding Faculty Leadership for the Development of Graduate Research Assistants." This award is presented to the faculty member who provided the greatest leadership in direct research advising and in using external resources to support Graduate Research Assistants during the period January 1, 2003 , to December 31, 2005. Professor Sitaraman also serves as the leader of the PRC’s research alliance on Reliability challenges and issues for the System-On-Package (SOP) electronics packaging concept.
Contact: suresh.sitaraman@mse.gatech.edu.

Patents & Inventions

Title: Integrated passive devices fabricated utilizing multi-layer, organic laminates
U.S. Patent Number: 7,068,124
Issued to: White; George E.; Swaminathan; Madhavan; Sundaram; Venkatesh; Dalmia; Sidharth
Issue Date: June 27, 2006
Notes: The present invention includes an organic device that can be integrated in a multilayer board made of organic material. The passive devices can be integrally fabricated on a circuit board in either surface mount device ( SMD ) or ball grid array ( BGA ) form. Alternatively, the passive device can be constructed in a stand alone SMD or BGA /chip scale package (CSP) form to make it mountable on a multilayer board, ceramic carrier or silicon platform in the form of an integrated passive device. The passive device includes side shielding on two sides in the SMD form and four sides in the BGA /CSP form. The side shielding can be external or in-built.

Title: Multi-Axis Compliance Spring
U.S. Patent Number: 7,011,530
Issued to: Suresh K. Sitaraman, Lunya Ma, and Qi Zhu
Issue Date: March 14, 2006
Notes: This patent deals with innovative off-chip interconnects to address next-generation semiconductor packaging needs. Dr. Lunyu Dennis Ma and Dr. Qi Angela Zhu are my past Ph.D. students who are currently working at Intel. This patent is a result of our work under a NIST/ATP collaborative agreement with Xerox/PARC and Nanonexus.

Publications
"Moore's Law Meets Its Match" An insightful article by Prof. Rao Tummala was published in the June 2006 issue of IEEE Spectrum, entitled “Moore’s Law Meets Its Match". The article explains that we have reached a new era in Systems Integration, compared to Transistor Density defined by Moore 's Law. Read the article online at http://spectrum.ieee.org/jun06/3649.

Team Member Highlight

First Time Motherhood for PRC Short Timer The PRC is happy to announce that Lauren Hall, PRC program manager, and her husband, Brian, are expecting their first baby on December 6, 2006 ! The excited parents-to-be decided to keep their baby’s gender a surprise. Only their ultrasonographer knows at this point. Lauren is noticeably happy about this new experience. And though we’ve not seen evidence of weird cravings, it’s only a matter of time before Brian will be shopping at 2 a.m. for pickles, Moose Tracks ice cream and roast beef! With her desk centrally located in the PRC’s main office, Lauren has become one of the busiest, most informed, and organized people at the PRC. She has become a valuable asset to PRC director, Rao Tummala, and the PRC team. Often called upon to wear several "hats", it’s not uncommon to see her at PRC events bright and early taking registrations, helping attendees, and setting up projection equipment. Family has always been important to Lauren which she has managed to balance well with her career endeavors. As she makes the transition to motherhood, we have no doubt that she will do a great job! Unfortunately for us, this means that she will be leaving the PRC. Her last day is will be August 31, 2006 . With only 31 days left (as of this writing) our "short timer" will be preparing for full-time employment at home. And we do mean "full time"! Lauren, before you leave, the PRC team would like to express a few of its collective thoughts. We'll miss your pleasant smile, sense of humor and laughter. We’ll miss being the beneficiaries of your remarkable organizational skills. Above all, we'll miss not having you as a part of the PRC family. All the best to you, your husband, and new baby!

PRC Attends 56th ECTC in San Diego
The PRC attended the 56th Electronic Components and Technology Conference (ECTC) from May 30- June 2, 2006 . The event was held in San Diego , California at the Sheraton Hotel and Marina . The PRC featured two Professional Development courses based on the SOP systems integration concept. "System-On-Package (SOP) vs. System-In-Package (SIP), and System-On-Chip ( SOC )” was presented by PRC director, Rao Tummala and PRC research director Mahadevan K. Iyer. The second course, “Recent Advances in Nano Polymeric Composites & Polymers for Electronic Packaging” was presented by Professor C. P. Wong, Wafer Level Packaging research alliance leader.

For information on conferences and workshops sponsored by the PRC, visit the PRC website at www.prc.gatech.edu

Professor Gee-Kung Chang
Byers Eminent Scholar Chair in Optical Networking
In this issue, we present Professor Gee-Kung Chang, faculty leader of the PRC Optoelectronics research alliance. Professor Chang joined the Packaging Research Center at Georgia Tech in 2002 after serving as Vice-president and Chief Technology Strategist of OpNext, Inc., where he was responsible for technology planning and product strategy for advanced optical networking devices and components. His wealth of experience includes optoelectronic and photonic subsystems, optical networks and next generation optical internet.

Professor Chang earned his bachelor degree in Physics from National Tsinghua University in Taiwan in 1969, and his doctoral degree from the University of California, Riverside, in 1976. He spent the following two years doing postdoctoral research in experimental electron/photon physics at Rutgers and Cornell University . Dr. Chang spent the next 23 years within the Bell Systems in New Jersey Bell Labs, Bellcore, and Telcordia Technologies where he served in various capacities including Director of the Optical Networking Systems and Testbed, Director of the Optical System Integration and Network Interoperability, and finally, Executive Director and Chief Scientist of the Optical Internet Research Group.

Professor Chang has been granted forty patents in the area of optoelectronic devices and packaging, high speed integrated circuits, telecommunication switching components and systems, WDM optical networking elements and systems, multiwavelength optical networks, optical network security, and optical label switching routers. He has co-authored over 200 peer-reviewed journal and conference papers. He is a Fellow of both IEEE LEOS and Optical Society of America.

A recent article published at Georgia Tech, "Hybrid Network Delivers Wired/Wireless Service" demonstrates one of the exciting Optoelectronics Systems developments he is involved in at Georgia Tech.

Spotlight on German TUD Student René Landgraf
René Landgraf, an intern visiting the PRC from Dresden University of Technology (TUD), gained valuable experience from Nov. 2005 to May 2006 as part of TUD's electrical engineering program. Then in his fifth year, his main interest was electronics packaging. A recent TUD project dealt with investigations on the applicability and printability of solder pastes and conductive adhesives in flip-chip packages.

Research in the PRC's Next Generation Substrate Laboratory involved passives and actives integration in high-density packages. Under Venky Sundaram's and Boyd Wiedenman’s guidance, he worked on the build up of a miniaturized inductor embedded in a multilayer module using a magnetic nano-composite material, involving lithography, screen printing and electroless and electrolytic copper printing chemical processes. His work also involved operating spin coaters, plasma processing, lithography, copper plating lines, lamination tools, as well as examining C-SiC as an alternative substrate material and optimization of a new electrolytic copper plating line involving atomic absorption spectroscopy, cyclic voltammetry stripping, and video microscopy.

Upon leaving René expressed, "Working in the substrate lab gave me the opportunity to gain excellent experience in state-of-the-art technologies of electronics packaging as well as cultural and linguistic experiences. I want to thank Prof. Tummala, Mr. Venky Sundaram and Mr. Boyd Wiedenman and the whole PRC staff for their support and guidance during the period of my work at the PRC. The internship was made possible by the expanding relationship between the Packaging Research Center and the Technical University of Dresden. I am very grateful for this opportunity."

René returned to Dresden where he is now working on his master thesis to graduate with a TUD master’s degree in early 2007.