SOP DESIGN

Power-Signal Integrity Co-Simulation for High-Speed Interconnects
Power and Signal Integrity co-simulation is essential for fast design closure. We developed a transient simulation methodology using S-parameters obtained either by measurement or by simulation. The interaction between transmission lines and supply planes is taken into account by using a novel modal decomposition method. This allows transient simulation of coupled/uncoupled microstrips referenced to non-ideal power planes. We also developed an explicit delay extraction methodology for transient simulation without violation of causality. Contact Madhavan Swaminathan, madhavan.swaminathan@ece.gatech.edu

Packaging of 2007 Microprocessors
Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers. We investigated the trade-offs between single and multi-core processors vs. their power, frequency, and bandwidths. Based on this study, we showed that the performance of a multi-core processor far exceeds single-core processors using a TeraByte/s application. We identified a possible packaging solution for such a multi-core microprocessor packaging for embedded decoupling, fine pitch interconnects and microvias to support such processors. Contact Madhavan Swaminathan, madhavan.swaminathan@ece.gatech.edu

Electromagnetic Bandgap Structures for Analog-Digital Converters
Current trend for ADC is towards obtaining high-speed and high-resolution. This trend makes ADC more sensitive to noise due to the reduction in noise and timing margin. Therefore, careful design of high-speed and high-resolution ADC test board becomes very important for managing the noise. The electromagnetic band gap (EBG) structure was suggested for managing the power/ground noise. A novel method called the current path approximation method (CPA-Method) was developed to synthesize high-isolation and ultra-wideband EBG structure. This method can reduce computational time for the design of EBG structures for a given band gap specification. The synthesized EBG with CPA-Method was applied to ADC test board. It showed significant power/ground noise reduction. Contact Madhavan Swaminathan, madhavan.swaminathan@ece.gatech.edu

RF Front End Module Development on LCP
The RF packaging and design laboratory has been working with novel, multi-layer organic processing technology. One such organic material used is the 3-D stack-up of low-loss Liquid Crystalline Polymer ( LCP) substrates. Design and characterization of embedded LNAs, VCOs, Mixers, Filters, Baluns, and Diplexers were accomplished. The modules were developed for many different systems ranging from Cellular band, 802.11a/b/g, 3G, and LMDS. In the recent past, a concurrent oscillator that simultaneously generates two harmonically-independent frequencies has also been successfully developed. Contact Madhavan Swaminathan, madhavan.swaminathan@ece.gatech.edu

Embedded Decoupling Capacitor Performance in High Speed Circuits
Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of high speed digital circuits because of its shorter leads that result in smaller parasitic inductance. A recent PRC study showed a number of other factors that are important: 1) Like a typical SMD capacitor, embedded capacitor can be equivalent to a L-C-R serial circuit in certain frequency bands. 2) Inductance of an embedded capacitor depends not only on the electrode geometry, size, feature, but also on the connection of via-through hole. 3) High dielectric constant ε r can reduce the impedance of embedded capacitor at low frequency band, while it shifts the first resonant frequency to low frequency band, and then lowers the performance at high frequency. 4) Patterned electrodes do not affect the impedance at low frequency band but affects the self-resonant region. 5) To design an efficient decoupling network, power-ground network, current, voltage, noise tolerance, connection- position, and frequency have to be taken into account. Contact Lixi Wan, lixi@ece.gatech.edu and Madhavan Swaminathan, madhavan.swaminthan@ece.gatech.edu

SOP FABRICATION

Thin-Film Embedded Capacitors in Printed Wiring Board Using Sol-Gel and Foil Transfer Processes
To support the growing need for embedded capacitor technology, PRC developed high dielectric constant ceramic films with capacitance densities over 1.5 μF/cm², loss 0.05 and breakdown voltage >7 V. These films, although processed at high temperature, are subsequently laminated onto printed wiring board with good yield and stable dielectric properties. This breakthrough in the embedded technology was achieved by exploring a modified sol-gel process to grow ultra thin films (~300 nm) on copper foils as carrier substrate .Contact Dr. Isaac Robin Abothu, robin@ece.gatech.edu; Prof. Rao Tummala, rao.tummala@ee.gatech.edu

Embedded Actives and Passives with “Chip-last But with Chip-first Benefits
Current embedded IC technologies are based on “chip-first” approach, where the chip or chips are mounted face up to a rigid block and an interconnect is built sequentially on top of the chip. In this chip-first approach, there are many manufacturing problems to be worked out to reduce costs and increase the yields. The PRC is proposing an embedded IC approach that it calls “chip-last approach with chip first benefits” to overcome the disadvantages of chip-first approach . For interconnections of embedded IC to the build-up layer, PRC’s nano-interconnect technologies are applied to enable shortest interconnections with the best electrical and yet with the best thermo-mechanical properties and fine pitch. Contact Baik-Woo Lee, baikwoo@ece.gatech.edu; Prof. Rao Tummala, rao.tummala@ee.gatech.edu

Wire-on-Bumps (WOB)
The WOB technology is a new PRC proprietary process for stacking memory chips without wire bonding which takes up space and which adds lot of inductance. The new PRC process utilizes the existing bonding technologies for vertical connection of peripheral bumps on chips. The WOB does not need interposers or, Si- through vias or complex interconnections that others have proposed, thereby leading to less complex assembly and lower cost. Currently, PRC is in early development stage with two types of prototypes based on this technology and the first demonstration of WOB technology is planned in September 2005. Contact: Chong Yoon, cyoon@ece.gatech.edu; Prof. Rao Tummala, rao.tummala@ee.gatech.edu

OPTOELECTRONICS

Defect-free, Nano-Smooth Polymeric Waveguides for Optoelectronic Systems Integration
A novel waveguide structure and process have been developed at the PRC. The new technology enables defect-free, nano-smooth, and high-definition polymeric waveguides and passive devices. Defects typically cause serious performance degradation of optical transmission. Manufacturability has been a big challenge in the industry to integrate optoelectronics into high-performance electronic systems. This new PRC technology allows fabrication of defect-free polymeric waveguides at low cost in the PCB environment. This new technology allows high definition polymeric devices as well such as MMI and switches, which need high precision structures. Contact Dr. Fuhan Liu, fliu@ece.gatech.edu; Prof. Rao Tummala, rao.tummala@ee.gatech.edu; Gee-Kung Chang, gkchang@ece.gatech.edu

WAFER LEVEL PACKAGING & ASSEMBLY

All-Polymer High K Materials for Embedded Capacitor Applications
The development of organic substrates with compatible high dielectric constant (K) materials has been a major challenge in the embedded capacitor technology. In this study, c onductive polymer-epoxy blends were developed as high K materials for embedded capacitor applications . To ensure better dielectric properties, an in-situ polymerization method was applied to prevent the agglomerations of conductive polymer particulates to achieve better dispersion. Remarkable increase in K value was observed due to the enhanced interfacial and electrode polarization effects caused by the incorporation of conductive polymer. Contact Fei Xiao, fei.xiao@mse.gatech.edu; C.P. Wong, cp.wong@mse.gatech.edu

Extending Pb-free Solder and Underfill Technology for Flipchip to Organic Substrates
Georgia Tech-PRC is proposing new ways to extend solder technology with underfill. As the I/O pitch becomes finer and finer so does the bump height, making underfill dispensing under large chips with particle-loaded underfills very difficult, without defects.

Effect of Polymer-Filler Interface on Thermal Conductivity of Electronic Packaging Composite Materials
Thermal conductivity measurements showed that the addition of 10 wt% alumina filler can enhance the thermal conductivity of polymer composites by about 23%, and the functionalization of alumina particle surface can further increase the thermal conductivity by another 6.5%. Both 85°C/85%RH temperature/humidity aging and -50°C ~ +80°C thermal shock testing showed almost negligible effect on the composite conductivity. Contact Fei Xiao, fei.xiao@mse.gatech.edu; C.P. Wong, cp.wong@mse.gatech.edu

Room-temperature Stable Underfill for Wafer Level Application
Commercial Underfill compositions are made by combining the epoxy resins and catalysts. Such materials have to be stored in frozen environments (usually -40°C) because combinations of epoxy resins with catalysts are generally not stable enough to be stored for any appreciable periods. We have started the research in the room-temperature-stable underfill formulation with latent catalysts. Special imidazolium salts were investigated as catalyst and the storage experiments are beginning to show the possibility of longer shelf life (up to 120 days) at room temperature with these novel latent catalysts. Contact Fei Xiao, fei.xiao@mse.gatech.edu ; C.P. Wong, cp.wong@mse.gatech.edu

RF

Novel Antenna for Wearable/Implantable Medical Devices
Wearable sensors capable of establishing real-time wireless links for monitoring vital life signs is the current trend in the healthcare industry. However, the major drivers for wireless links are form factor, cost, weight and data security and reliability. Paving toward these targets, the RF Alliance has designed and implemented a novel folded shorted patch antenna structure with reduced overall length by a factor of eight as compared to conventional patch antenna and by a factor of two as compared to a conventional shorted patch antenna on an LTCC platform. The antenna shows nearly omni-directional radiation pattern which is essential for unrestricted movement of patients to be monitored and an impedance bandwidth of 4% enabling high-speed data transmission. The antenna was designed for ISM band (2.4 – 2.483 GHz) as well as IEEE 802.11a (5.8GHz) and LMDS (28GHz) bands. Such antennas can be used for monitoring critical body signals and other passive implantable devices. Contact Bo Pan,panbo@ece.gatech.edu; Manos M. Tentzeris, tentzeris@ece.gatech.edu ; J.Papapolymerou, papapol@ece.gatech.edu

Reconfigurable Smart Antenna for Mobile Electronics
The multitude of different standards in cell phones and other personal mobile devices require compact multi-band and smart antennas with reconfigurable features. The reconfigurable Annular Slot Antenna (ASA) developed in this quarter operates at three frequencies with the central frequency being at 5.8 GHz, with a reconfigurable radiation pattern. It is fabricated with low cost materials to a compact design, suitable for integrating in mobile systems. The RF Alliance developed for the first time an annular slot antenna with simultaneous frequency and radiation pattern reconfigurability, by using pin diodes at pre-determined locations and to reconfigure the matching circuit. For this antenna, only one frequency resonates at a time, which is desirable when there are power or interference issues. Contact Simos Nikolaou, simos@ece.gatech.edu; John Papapolymerou, papapol@ece.gatech.edu; Manos M. Tentzeris, tentzeris@ece.gatech.edu

RFID Tag for High Volume Consumer Products
The PRC RF Alliance developed three novel, single-layer and double-layer miniaturized antennas for 915 MHz RF ID tags that are designed to be embedded inside commercial automobile tires. The power required to energize and activate the tag’s microchip is drawn from the EM field, provided by the reader unit’s antenna. The transponder IC stores the tire's unique ID information such as when and where the tire was made, its maximum inflation pressure, size and so on. The tag utilizes low cost lead frame- based IC packaging process and the miniaturized antenna is built in the lead frame. For the first time, the antenna efficiency has been raised to >80% with an RFID size less than 3in x 3in and RFID range by a factor of 3 to 5. Contact Serkan Basat, gte309k@mail.gatech.edu; S.Bhattacharya, swapan@ece.gatech.edu; Manos M. Tentzeris, tentzeris@ece.gatech.edu

THERMAL MANAGEMENT

Compact Thermosyphon Performance Enhancement Using Water at Reduced Pressure as the Working Fluid
Liquid cooling with phase change is a very attractive option for thermal management of electronics because of the very high heat transfer coefficients achievable. Two-phase liquid cooling can be implemented in a thermosyphon loop, which has an evaporator, where heat is absorbed from the source during boiling of the working fluid, and a condenser, where the absorbed heat is rejected. Water is a preferred working fluid for boiling heat transfer due to its excellent thermal properties. Using water at sub-atmospheric conditions helps in initiation of boiling at low temperatures, which is necessary for electronics cooling applications, often limiting the maximum temperature to 85 ˚ C for silicon devices. Past studies have also shown that using boiling enhancement structures improve heat transfer by lowering the incipience overshoot, increasing heat flux and reducing evaporator volume. However, detailed study on the effects of enhancement structures and subatmospheric saturation conditions on the boiling of water in a compact thermosyphon loop were lacking in the literature. Experiments were carried out in a thermosyphon setup at 9.7, 15 and 21 kPa saturation pressures for two different enhancement structure geometries at varying heat loads. The experimental investigation showed that very high heat fluxes (~105 W/cm2 ) can be achieved by boiling at sub-atmospheric pressures with enhancement structures. Contact Professor Yogendra Joshi, Yogendra. joshi@me.gatech.edu

Reduced Order Modeling of Steady Turbulent Flows in Electronic Systems
In the characterization and design of complex distributed parameter fluid systems, detailed experimental measurements or fine numerical calculations often produce excessively large data sets, rendering more advanced analyses inefficient or impossible. The proper orthogonal decomposition (POD) has been successful in creating low dimensional dynamic models of turbulent flows. In recent research, its utility is extended to produce approximate solutions of steady, multi-parameter simulations within predefined limits. The results indicate that a new flux matching procedure can reduce the model size by 4 orders of magnitude while adequately describing the airflow transport properties within engineering accuracy. The results showed that a full computational fluid dynamics model could be approximated with less than 10 degrees of freedom for a 104 compression in model size and produce results within 5% of the true solution. Contact Professor Yogendra Joshi, Yogendra.joshi@me.gatech.edu