PRC Invites Companies Interested in 3DASSM to its Final Workshop, Sept. 17-18, 2008 at Georgia Tech

This will be the final workshop at Georgia Tech on Sept 17-18, 2008 for those interested.

Benefits from this program

Georgia Tech is proposing, in partnership with Fraunhofer (Germany) and KAIST (Korea), a consortium that goes beyond 3D but   with a focus on  lower-cost Through-Silicon Via (TSV) and 3D stacking technologies, leading to an all silicon functional module and system. This is what is referred to as 3DASSM, a 3D All Silicon System module, a global industry-academia consortium on a global topic with potential to become a disruptive and revolutionary silicon module technology in the near term and a systems technology in the long term. The ultimate vision is a highly miniaturized all-silicon-wafer system for ICs, packages and boards.

3DASSM will  explore and develop advanced electrical and mechanical designs, advanced materials and processes, thin film components, ultra thin highly integrated packages, system interconnections, and seamless integration of all these into wafer level modules and systems.

The global academic partners participating in this consortium are Prof. Herb Reichl's Fraunhofer, Berlin and Munich teams, Prof. Joungho Kim's KAIST team, and Prof. Tummala's Georgia Tech PRC team.

Three Ways to Join

1. Full Membership–Fundamental Research:  More than 20 Fundamental and building block research projects.
2. Full Membership–Fundamental and Integration Research: 3 Integration and demonstrators Low cost TSV stack, Silicon package replacing organic package and seamless integration of IC and package.
3. Supply Chain Membership: For development of manufacturing infrastructure for materials, process and design tools.

Membership Benefits: Technical, Infrastructure, and Financial

Short Term Benefits: In the first two years, companies can benefit by applying to their needs from fundamental research as well as from integration a research in low-cost TSV, 3D stack bonding and silicon package replacing organic package.

Mid Term Benefits: In the next two years, further advances in fundamental integration and research, leading to seamless integration of Silicon ICs and packages into a single monolithic silicon module with TSV, 3D stack bonding, advanced and lower cost embedded thin film components and silicon package to board interconnections.

Long Term Benefits: The long term vision of All Silicon System will be delivered in the third phase.

Investment Benefit: Another benefit is the leveraging of company membership funds by a factor of about 20X. The consortium proposes to carry out more than 20 fundamental research projects, each at a cost of $125-150K per year and three integration projects at a cost of about $2 M per year. This adds up to a total of approximately $5 M per year. The membership fee proposed for each company, however, will be a factor of 20-30X less than this total investment.

Expertise Benefit: Companies can expect to receive the outstanding expertise and facilities of the consortium members at Fraunhofer IZM, Georgia Tech PRC and KAIST. They are among the most well known academic organizations in the world, with the best facilities to carry out the proposed 3D and beyond research.

Global Industry Response

Industry response in the proposed consortium is very high with 80 attending the Georgia Tech workshop in March 2008; 30 attending the Berlin workshop in May 2008, and more than 100 in Seoul and Tokyo workshops in July 2008.

Executive White Paper for Those who are interested

An executive white paper proposal is available for those companies interested in joining the consortium. Please contact any of the following 3DASSM leaders for a copy:

US and Worldwide
Prof. Tummala (rtummala@ece.gatech.edu )
Prof. Swaminathan (madhavan.swaminathan@ece.gatech.edu)
Dr. Chatterjee (ritwik@ece.gatech.edu)

Europe
Prof. Reichl (herbert.reichl2@izm.fraunhofer.de)
Dr. Aschenbrenner (Rolf.Aschenbrenner@izm.fraunhofer.de)

Korea
Prof. Joungho Kim (joungho@ee.kaist.ac.kr )
Dr. Kim (jskim@ee.kaist.ac)

Japan
Yutaka Tsukada (YuTsukada@aol.com)

Georgia Tech Presents Record Number of Papers and Posters at IEEE ECTC 2008
Georgia Tech and the Microsystems Packaging Research Center received outstanding recognition at the Electronic Components and Technology Conference (ECTC) held at Disney's Contemporary Resort in Lake Buena Vista Florida, May 28-29, 2008. A total of 28 papers were presented   to showcase advances in design, materials, embedded components, interconnections and biosensors several of which won outstanding and best paper awards. For the complete list, visit http://www.prc.gatech.edu/ectc08

Georgia Tech PRC Student Wins Prestigious IEEE CPMT Best Student Paper!
Tapobrata Bandyopadhyay, a graduate student in ECE advised by Prof. Tummala and Prof. Swaminathan, winner of the 2008 IEEE-CPMT $10,000 Ph.D. Student Fellowship Award for best student paper presented during the Electronic Components and Technology Conference (ECTC) held May 27-30, 2008 in Orlando, Florida.

Mr. Bandyopadhyay's paper, "Microwave Design, Fabrication & Characterization of a Novel Nano-Cu based Ultra-fine Pitch Chip to Package Interconnect" presented, for the first time, the RF/Microwave design, modeling, parametric optimization and characterization of interconnect transitions for a Nano-Cu based chip-to-package interconnect system for microelectronics packaging applications. His work demonstrated lower electrical parasitics and transition losses (for Chip-on-Chip and Chip-on-Package configurations) using Nano-Cu interconnects, as compared to conventional Solder bumps and Gold stud bumps.

The winning paper was selected from among 7 competing finalists by a 5-member fellowship committee who collectively voted his paper as the best! Congratulations. The co-authors of this paper are co-advisors Prof. Tummala, Swaminathan and Dr. Mahadevan K. Iyer, formerly of GT and now Infineon Technologies and Dr. P.M. Raj, Gaurav Mehrotra.

Mr. Bandyopadhyay will receive a one-year Fellowship of $10,000 towards his Ph.D. studies in 2008 and 2009 and is eligible for up to $300 towards his travel expenses that are not paid from another source.

Congratulations again on this accomplishment!

Japan and Korea Workshops for 3D All Silicon System Module (3DASSM) Consortium
The Microsystems Packaging Research Center, Fraunhofer Institute (Berlin), and the Korea Advanced Institute of Science and Technology (KAIST) held two workshops on 3DASSM, one in Tokyo, Japan and the other in Seoul, Korea in July.  There was a strong industry interest and the program continues toward its launch on October 1, 2008.  A pre-launch program finalization meeting is planned for September 17-18, 2008 at the Georgia Institute of Technology in Atlanta, Georgia, USA.  If you are interested in joining 3D-ASSM consortium, please plan to attend this meeting to shape the final program.

To learn more about 3DASSM, visit www.prc.gatech.edu/events/3dassm.

September 2008 Industry Week at Georgia Tech Microsystems Packaging Research Center
September 15-19, 2008 is the week-long series of consortia programs. Included with the well-established programs such as MSDT, TIM, and EMAP which are meant for participating members, are two new industry consortia development workshops that are open to public that will focus on 1) ultra-miniaturized bio-electronics with System-on-Package technologies (BioSOP), and 2) Next Generation of flipchip  with advances in substrate, its warpage reduction, interconnections and assembly. Both workshops are free of charge and open to all interested industry representatives. Lunch will be provided. See the following two news items for additional information on other PRC Industry Week programs.

Industry Week At-A-Glance: http://www.prc.gatech.edu/events/glance

PRC Proposes an Industry Consortium on Ultra-miniaturized Bioelectronics Systems using its System-On-Package Concept (BioSOP)
The Microsystems Packaging Research Center at the Georgia Institute of Technology is organizing a workshop on "Bioelectronic System-On-Package (BioSOP)", as part of its Industry Week, September 15-17, 2008. The BioSOP workshop, led by Georgia Tech faculty Prof. Maysam Ghovanloo and Dr. Raj Pulugurtha, will begin on Thursday, Sept. 18th and will focus on the impact of emerging SOP-based integration for highly miniaturized systems combined with emerging nanomaterials and nanotechnologies on implantable biomedical devices and biosensors.

A key objective of the workshop is to bring together leading biomedical system applications, semiconductor, packaging and materials companies and identify key fundamental building block technologies that can address the long-term need of implantable biomedical devices.

This workshop will focus on recent advances in the following areas:

1. Bioelectronic Systems and Design,
2. Bio and Chemical Sensors Integration,
3. Bio-compatible Substrates, Hermetic Packaging,
4. Neurostimulators: Material Strategies to Modulate Tissue and Neural Response,
5. Embedded Power Sources, and
6. Embedded Thin ICs and Passives.

Leading academic faculty from Georgia Tech and industry leaders in biomedical devices and packaging will participate and present in this workshop. Senior engineers, technical managers and technical directors and leaders from semiconductor, packaging, materials, and biomedical system integration companies are expected to benefit from this workshop.

An agenda for this workshop will be circulated the week of August 4th.

If you are interested in attending this workshop, please register at the website http://www.prc.gatech.edu/events/biosop.

PRC Proposes an Industry Consortium on  Next Generation Flipchip with Advances in Substrate, Warpage Reduction, Interconnections and Assembly
The PRC will sponsor its first Industry-Academia consortium workshop on “Next Generation Flip-Chip: Substrate, Warpage, Interconnects and Assembly” (NGFC), on September 19, 2008 during Industry Week (Sept. 15-19, 2008). For further information and online registration, please visit www.prc.gatech.edu/events/ngfc.

Georgia Tech Hosts JISSO International Council (JIC) Workshop
IPC and the Jisso International Council (JIC) sponsored a technical seminar on May 21-22, 2008 to provide information on the latest trends in interconnection technologies used in electronic products. Held in conjunction with the 2nd Jisso International Forum hosted by the Georgia Institute of Technology, the technical seminar was hosted by the Microsystems Packaging Research Center. Members of JIC, as well as technology leaders from industry spoke on environment-friendly manufacturing, three-dimensional integration, interposer substrates, and standards activities. The PRC presented its vision of packaging for the next decade as well its current and future industry consortia such as embedded actives and passives and all silicon systems.

Photos: http://www.prc.gatech.edu/jisso08/images

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Industry-PRC Consortia Development:
www.prc.gatech.edu/consortia