Georgia Institute of Technology Packaging Research Center An NSF Engineering Research Center Leading the SOP & Nano Packaging Revolution
	e-newsletter Vol. 1, Issue 1 – January 2004

System-on-Package (SOP), being pioneered by the Packaging Research Center (PRC) is about cost–effective and miniaturized heterogeneous systems. The Intelligent Network Communicator (INC) system testbed with embedded digital, RF, and optical functions, was successfully demonstrated during the National Science Foundation’s (NSF) visit with the PRC.

The INC testbed project is the symbolic showcase of the SOP concept and has been driven by the PRC since 2001. The goals and objectives of the INC system testbed are to explore new systems architectures enabled by multifunction SOP technologies. The SOP concept is now beginning to be widely accepted and deployed as the key solution for low-cost, multi-functional electronic systems, especially for wired and wireless communications applications. The PRC believes that the SOP approach is more appropriate for such applications than System-on-Chip (SOC). The INC demonstration included architecture and design, materials, processes, fabrication, integration, test, and assembly using the PRC's new SOP technologies, in collaboration with its new industry partner, Endicott Interconnect Technologies of Endicott, N.Y. The INC system was rigorously tested by each subsystem group (RF, Digital, and Opto) before the real-time demonstration. For further information, please contact Prof. Rao Tummala (rtummala@ece.gatech.edu), or Dr. Kyutae Lim (ktlim@ece.gatech.edu).

This Month’s Research Focus: Embedded RF
 
RF Tools and Models
The RF/IP Alliance has performed extensive research in the area of RF tools and models. The most recent highlights include the development of a hybrid electromagnetic and mechanical full-wave time-domain simulator that can be used for the efficient modeling of 3D integrated RF modules (Cellular, WLAN802.11x, LMDS) as well as of the transient and steady-state of packaged RF MEMS. Also, they have developed hybrid statistical/EM and Genetic Algorithm/EM techniques for the optimization of complex RF/Wireless/Sensor packages up to mm-wave frequency range. In addition, the RF/IP thrust recently developed models for materials that can be laminated and can thus be used for multi-layer SOP-based transceivers. Specifically, LTCC, MLO, and LCP have been investigated and characterized up to the mm-wave frequency range. Transmission lines, filters, 2D/3D passives, and packaging-adaptive antennae have already been designed for these types of materials and are currently in the stage of design for novel materials, such as metamaterials. For more information, please contact the leader of the RF/IP Alliance, Prof. Manos Tentzeris (etentze@ece.gatech.edu).

An Ultracompact Printed Antenna for WiFi, GPS, Cellular, Sensor and mm-Wave Applications
A novel ultracompact printed antenna for applications ranging from GPS to mm-wave short-range broadband is being developed by the RF Alliance at the PRC. The use of Soft-and-Hard Surface (SHS) rings around the patch antenna allows for its miniaturization by a factor 2-4/dimension (significantly smaller than the EBG approach), improved efficiency for high-k substrates by up to 90%, and enhancement of gain by 6-12 dB. In addition, the whole architecture is completely compatible with multilayer ceramic and organic modules and allows for the easy integration with cavity-shielded MMICs. The use of stacked patches in different layers provides a bandwidth up to 8-10% even for high-dielectric materials (ε_r > 8). This approach has already been used in 2x2 flexible antenna arrays for space, automotive, communication and sensor modules. The ongoing effort focuses on the extension of the design to UWB applications under the framework of an integrated UWB SOP-prototype being currently developed and fabricated by the RF Alliance. For more information, please contact Prof. Manos Tentzeris (etentze@ece.gatech.edu), or Prof. Joy Laskar (jlaskar@ece.gatech.edu).

Recent PRC Publications on RF
1. G. Ponchak and E. M. Tentzeris, "Finite Ground Coplanar Waveguide (FGC) Low Loss, Low Coupling 90-Degree Crossover Junctions", IEEE Transactions on Advanced Packaging, Vol. 25 No. 3, pp. 385-392, August 2002.

2. C. H. Lee, A. Sutono, S. Han, K. Lim, S. Pinel, J. Laskar and E. M. Tentzeris, "A Compact LTCC-based Ku-band Transmitter Module", IEEE Transactions on Advanced Packaging, Vol. 25 No. 3, pp. 374-384, August 2002.

3. D. Staciulescu, J. Laskar and M. M. Tentzeris, "Design of experiments (DOE) technique for microwave/millimeter wave flip-chip optimization", International Journal of Numerical Modeling, Vol. 16, pp. 97-103, 2003.

4. M. M. Tentzeris, "Full-Wave Methods for the Analysis, Modeling and Design of RF and Microwave Geometries", Invited Chapter for the book: ``The RF/Microwave Applications: Challenges and Solutions", edited by M. Golio, pp. 18.1-18.32, CRC Press, June 2003.

5. K. Kawano, N. Miura, M. Kuroda and M. M. Tentzeris, "A Novel Numerical Approach for the Analysis of MEMS-Based Variable Capacitors with Moving Metallic Plates"-in Japanese, Asian Fonts required, The IEICE Transaction on Electronics, Vol. J87-C, No. 1, pp. 32-38, January 2004.

6. J. Xu, C. P. Wong, “Ultra High-k Polymers for Embedded Passives Applications”, Encyclopedia of Smart Materials, John Wiley and Sons, New York, 2003.

7. H. Windlass, P. Raj, D. Balaraman, S. Bhattacharya and R. Tummala, “Polymer-Ceramic Nanocomposite Capacitors for System-On-Package (SOP) Applications”, IEEE Transactions on Advanced Packaging, Vol. 26, No. 1, pp. 10-16, 2003.

8. H. Windlass, P. M. Raj, D. Balaraman, S. Bhattacharya and R. Tummala, “Colloidal Processing of Polymer Ceramic Nanocomposites for Integral Capacitors”, IEEE Transactions on Electronics Manufacturing, Vol. 26, No. 2, pp. 100-105, April 2003.

9. Y. Rao, S. Ogitani, P. Kohl and C. P. Wong, “Novel Polymer-Ceramic Nanocomposite Based on High Dielectric Constant Epoxy Formula for Embedded Capacitor Application”, J. Applied Polymer Science, Vol. 83, pp. 1084-1090, 2002.

10. Y. Rao, J. Yue and C. P. Wong, “Materials Characterizations of High Dielectric Constant Polymer-ceramic Composite for Embedded Capacitor for RF Application”, Active and Passive Elec. Comp., Vol. 25, pp. 123-129, 2002.

11. Y. Rao, A. Takahashi and C. P. Wong, “Di-block copolymer surfactant study to optimize filler dispersion in high dielectric constant polymer-ceramic composite”, Composites, Part A: Applied Science and Manufacturing, Vol. 34, No. 11, pp. 1113-1116, November 2003.

PRC Organizes SOP Papers with a Special Issue in IEEE Transactions on Advanced Packaging

SOP technology started at Georgia Tech’s PRC in late 1994, funded by NSF, Georgia Research Alliance and electronics companies. It is about overcoming the shortcomings of SOC and current packaging, which are bulky and have low performance. It is also about microminiaturization of products. SOP does this by embedding components which are currently at bulky scale to micro scale in the short term, and to nano scale in the long term.

Today, SOP R&D is pervasive. An indication of this can be seen in the upcoming May issue of IEEE Transactions on Advanced Packaging. This issue will be a special one, devoted solely to the topic of SOP and its variations. You’ll find a total of 19 invited papers, each of which has been written at a high level but with a tutorial slant. This culmination of papers covers a broad range of SOP topics from a global perspective by authors from around the world and from design to fabrication, integration, test, assembly, thermal, and reliability. It’s our hope that you’ll enjoy this special IEEE Transactions on Advanced Packaging and, as always, we welcome your feedback.

Introduction
• Prof. Rao R. Tummala (Georgia Tech): “What is SOP and Why?”

SOP and SIP and 3-D Concepts
• Dr. Karl F. Becker (Fraunhofer Inst., Germany), et al: “Stackable System-in-Packages with Integrated Components”
• Dr. Mahadevan K. Iyer (IME, Singapore), et al: “Design & Development of Optoelectronic Mixed Signal System on Package (SOP)”
• Prof. Rao Tummala (Georgia Tech), et al: “Build-up SOP”

SOP Design
• Dr. Madhavan Swaminathan (Georgia Tech), et al: “Design of Power Distribution Networks – Status and Challenges”
• Dr. Peter Hofstee (IBM): “Future Microprocessors and Interconnect”
• Toshio Sudo (Toshiba, Japan), et al: “Electromagnetic Interference of System-On-Package (SOP)”

SOP Integration Technologies
• Dr. Li-Rong Zheng (Royal Inst. Of Technology, Sweden), et al: “Cost and Performance Trade- offs for Radio and Mixed-Signal System-on-Package Design”
• Prof. Rao R. Tummala (Georgia Tech) & Venky Sundaram (Georgia Tech), et al: “Advances in Microvia Dielectrics and Conductor Materials and Processes”
• Prof. Manos Tentzeris (Georgia Tech), et al: “3D Integrated RF and Millimeter-waves Functions and Module Using System-on-Package Technology”
• Prof. Richard Ulrich (Univ. of Arkansas): “Embedded Resistors & Capacitors for Organic-Based SOP”
• Steven Brebels (IMEC, Germany), et al: “SOP Integration and Co-design of Antennas”
• Prof. Nan Jokerst (Duke University), et al: “Planar Lightwave Integrated Circuits with Embedded Actives for Board and Substrate Level Optical Signal Distribution”
• Prof. Gee-Kung Chang (Georgia Tech), et al: “Optoelectronic Integration and Interconnection for Large Scale Mixed Signal SOP Platform”

Thermal
• Prof. Avi Bar Cohen (Univ. of Maryland) & Mehmet Arik (GE Global Research Center), et al: “Thermal Modeling and Performance of High Heat Flux SOP Packages”

Nano Wafer Level Packaging & Assembly
• Prof. Andrew Tay (NUS, Singapore), et al: “Nano Wafer Level Packaging of SOP”

Mixed Signal Test
• Prof. Abhijit Chatterjee (Georgia Tech), et al: “Low Cost Test of Embedded RF/Analog/ Mixed-Signal Circuits in SOPs”

Mixed Signal Reliability
• Prof. Suresh K. Sitaraman (Georgia Tech), et al: “System-level Reliability Assessment of Mixed-Signal Convergent Microsystems”

Manufacturing
• Prof. Gary May (Georgia Tech): “Intelligent SOP Manufacturing”

Endicott Interconnect Technologies Inc. (EI) has announced that it has entered into a strategic partnership with the Packaging Research Center (PRC) to develop and manufacture new packaging concepts for the electronics industry.
 
The PRC’s SOP concept, which integrates RF, optical and digital functions into modules or microminiaturized boards, enables the total convergence of computer, communication, and consumer functions into single packages or modules. The PRC utilizes its 300-mm SOP fabrication facility with a special focus on organic materials. EI will draw on its legacy of scaling fundamental research into commercial products to translate the efforts into early user hardware and volume production. In SOP, the package is the system and the system is more than a computing, communications, bio-medical, or consumer system. It’s all of these in one little package. “EI and the PRC are ideal partners for pioneering of SOP research, development, and commercialization.” says Professor Rao Tummala, the PRC director.
 
“Providing the electronics industry with solutions that will enable revolutionary change is a key focus for our company,” stated James J. McNamara, president and CEO, Endicott Interconnect Products. “Partnering with Georgia Tech will provide the avenue for EI to work with an academic leader in development and implementation of technology that will address the strategic needs of the industry."
 
Funding for the PRC is provided by the National Science Foundation and the State of Georgia to bring about new paradigms in the packaging of convergent microsystems, development of novel education programs for a new breed of highly skilled workers, and collaboration with industry for the benefit of US competitiveness. Each party will contribute both expertise and resources to the relationship. For further information, please contact Carl Rust (carl.rust@ece.gatech.edu).

PRC Offers a Comprehensive Set of Short Courses on Next-generation Microsystems Packaging Technologies

The week long course series, planned to be offered the week of May 24-28, 2004, consists of individual modules taught by highly respected Georgia Tech faculty. The individual modules are based on the PRC’s System-on-Package (SOP) vision, which integrates not only digital but also analog, RF, optical, and MEMS functions into one ultra-compact and low-cost packaging system to serve the needs of convergent telecom, consumer, and computer systems of the next decade. The SOP paradigm changes the current chip-centric or SOC system design methodology to a cheaper and faster-to-market systems-on-package-centric design flow. Attendees can register for one or more of the following modules:

• Nano-packaging
• System-on a Package, SIP, and SOC
• RF/Wireless Packaging: Status and Challenge
• Optoelectronics Packaging
• MEMS Packaging and Applications
• Embedded Passives
• Next Generation Microvia (Hands-on)
• Wafer Scale Packaging
• Low Cost Flip Chip Processing and Analysis (Hands-on)
• Thermal Management of Microelectronic Devices
• Polymers for Microelectronics: Process and Characterization
• Thermomechanical Reliability
• Signal Integrity

Detailed information will be available on the PRC web site, www.prc.gatech.edu, after February 15.

IEEE–CPMT and PRC Stimulate Emerging Nano and Bio-Packaging Technologies by Means of Nano-Bio Workshop

First International Nano Bio-Electronics Packaging Workshop • Atlanta, Georgia U.S.A. • March 22-23, 2004 • www.prc.gatech.edu/nanobiopack

This workshop will take place at the Grand Hyatt Hotel in Atlanta, Georgia. It will focus on Nano and Bio Packaging including Nano Package Design, Bio-Packaging, Sensor Packaging, Packaging Materials & Processes: Dielectrics, Capacitors & Fluidics, Nano Interconnections and Wiring, Thermal Science, Optical Interconnections, and Batteries.

The plenary session includes such keynote speakers as Dr. Meyya Meyyappan, Director, Center of Nanotechnology at NASA, Dr. Neal Shinn, Center for Integrated Nanotechnologies at Sandia National Labs, Prof. Buddy Ratner, Director, Engineered Biomaterials Research Center, University of Washington, Dr. Iwona Turlik, Vice President, Motorola, Prof. Mark Humayun, Director, Biomimetic Micro Electronics System Center, University of Southern California.

Technical sessions will include a variety of topics given by notable experts such as Nano Photonics by Avi Bar-Cohen, University of Maryland, Nano Imprint Processing by Randy Rannow, Hewlett-Packard, Nano Wafer Level Packaging by Andrew Tay, National University of Singapore, Nano Bio-Packaging by Jorma Kivilahti, Helsinki University of Technology, Nano Manufacturing by Srinivas Rao, Solectron, NEMS & Sensors by Kuoning Chiang, NTU, Taiwan, Nano Materials & Processes by Goran Matijasevic, University of California Irvine, and Nano Fluidics by Michael G. Wahl, Universität Siegen Germany.

The workshop is chaired by Professor Rao R. Tummala of the Georgia Institute of Technology. The International Planning Committee consists of Thom Fischer and Raj Chanchani of Sandia Labs (USA), Douglas Lowndes, ORNL (USA), Lee Loke Chong, Mahadevan Iyer and Andrew Tay (Singapore), Herb Reichl, IZM (Germany), Jim Morris and Ken Gilleo (USA), Johan Liu, Chalmers University (Sweden), Shen-Li Fu (Taiwan), Avi Bar-Cohen, Univ. of Maryland (USA), Srinivas Rao, Solectron (USA), Bruce Kim, Arizona State Univ. (USA), Walt Trybula, Sematech (USA), Ajay Malshe and Bill W. Brown, Univ. of Arkansas (USA).
For further information and registration please visit the workshop web site, http://www.prc.gatech.edu/nanobiopack.

BIST Funding to Georgia Tech PRC

A collaborative medium-scale National Science Foundation ITR proposal on BIST (Build-In Self Test) of Multi-Gigahertz Electronics was funded for $1.1M over a three year period. It includes Abhijit Chatterjee (PI) and co-PIs Prof. J. A. Abraham (Univ. of Texas, Austin), Adit Singh (Auburn), and Bill Eisenstadt (Univ. of Florida). This contract will bring about $300k to Georgia Tech over the next three years for PRC test research.

IEEE Recognizes Prof. Tummala’s Contributions in Reforming Microsystems Packaging Education

The IEEE Educational Activities Board (EAB), at its meeting in Seattle on November 14th, recognized Professor Rao R. Tummala for his exceptional achievements in education. Professor Tummala’s award, the IEEE Educational Activities Board Major Educational Innovation Award, was presented with the following citation:

"for reforming Microsystems Packaging education by unparalleled, systematic and innovative approaches to courses, curricula, tracks, books, degrees and workshops/conferences while mentoring and catalyzing other centers of excellence around the world."

Georgia Institute of Technology Packaging Research Center
- An NSF Engineering Research Center -
Leading the SOP & Nano Packaging Revolution

For further info, please visit: http://www.prc.gatech.edu

PH: 404-894-9097, FAX: 404-894-3842 • 813 Ferst St., MaRC Bldg. 351 • Atlanta, GA 30332-0560

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