| Books on Emerging Technologies from PRC: Book
on SOP
After a very successful publication
of first text book from PRC—"Fundamentals
of Microsystems Packaging,” which is now used by 51 universities
around the world, the PRC is now embarking on bringing out the first
book on SOP, comparing it to SIP and SOC. "Introduction to System
On Package" which will cover the concepts of SOC, SIP and SOP, followed
by 9 chapters on various topics that constitute SOP, essentially highlighting
the research accomplishments of PRC and the community over the past ten
years. The Chief Editor is Prof. Rao R. Tummala with authors from Georgia
Tech, other universities and industry. The book is slated for publication
by McGraw-Hill by December 2006. (Contact Mahesh Varadarajan: mahesh@ece.gatech.edu)
PRC Shares Research Results and Future Directions with its
IAB Members
The Packaging Research Center (PRC) recently held its
semi-annual Industry Advisory Board (IAB) on March 3-4 where the most recent
advanced microelectronics packaging and integration research results were
shared with the Center's industry partners. In addition, time was also
devoted to identifying possible new research directions and topics. Below
is a list of topics and the name of the person that came from this discussion,
to be considered by PRC:
Selective Research Accomplishments of PRC
High
Density Wiring and Low Loss Dielectrics
PRC has recently
demonstrated 6-10um lines and spaces and 20um microvias in low loss BCB
dielectric for ultra-high density SOP substrates. A novel process for
low-cost additive metallization of BCB with plasma surface treatment
and electroless and electrolytic copper plating has been developed. This
multilayer wiring process has been implemented on low CTE, high modulus
C-SiC composite and high Tg organic laminate substrates. Prototype multilayer
package substrates for 50 to 100um pitch flip-chip interconnects are
under development. (Contact Venky Sundaram: vsunda@ece.gatech.edu)
Embedded Passives
The PRC and Endicott Interconnect Technologies
have partnered in design and fabrication of an 8-layer SOP prototype
with embedded passive components to the specifications provided by the
Telecom Industry. Thin film resistors on a carrier copper foil as well
as polymer thick films were used for resistors in the range of 25 ohms
to 100 kohms. The capacitors were polymer-ceramic nanocomposites with
capacitance in the range of 0.1 to 2 nF/cm 2 and were designed to function
up to 5 GHz. The objective of this study was to show the manufacturability
of multi-layer multifunction SOP and address issues related to reproducibility,
reworkability, yield, tolerance, and thermo-mechanical reliability. In
Phase II of this project, PRC and EI Technology expect to work with numerous
materials companies to identify niche materials and processes for future
digital and RF applications. (Contact Dr. Swapan Bhattacharya: swapan@ece.gatech.edu)
Novel
Rigid Composite Substrate Technology
PRC, in collaboration
with Starfire Systems, initiated the ceramic composite substrate technology
program in 2002 to develop new rigid substrates with unique set of properties
not available today. The proprietary polymer-derived rigid substrate
technology enables high stiffness with Si-match CTE without compromising
large-area processability and cost. With these new composite boards,
flip chip reliability without underfill was demonstrated using 200 micron
pitch, 5 mm size test chips using thin BCB and low CTE PPE dielectrics.
Although low CTE boards increase the dielectric stresses in the build-up
layers, with proper thermomechanical design, >1000
cycle microvia and dielectric reliability was demonstrated with Cu/BCB
build-up layers. Advanced prototypes opto 2 cm die and 50-100 micron
pitch interconnects are now under evaluation. (Contact Dr. Raj Pulugurtha: raj@ee.gatech.edu)
New Research Focus
PRC Proposes Embedded Actives and Alternatives in its SOP and SIP
Approach
In “Embedded-Active” technology, thinned active
chips are integrated in a ceramic or organic substrate and interconnect
layers are formed to the active components. This technology creates new
opportunities to increase performance, functionality and packing density
by:
- providing short connections to the chip, which can reduce noise,
signal delay and power consumption, and enhance performance to the
GHz range,
- facilitating the integration of heterogeneous devices,
signals and materials, and
- reducing footprint occupied by package on board
and enabling 3D packaging technologies easily.
Despite its compelling potential advantages, embedded active technology
has been limited by a number of factors such as electrical and mechanical
design, process for interconnecting and embedding ICs, thermal issues
andthermo-mechanical reliability. At PRC, a team of people with the above
expertise are proposing to solve the problems as well as propose alternatives.
(Contact Dr. Baik-Woo Lee: baikwoo@ece.gatech.edu)
Industry-Academic Workshop on Packaging of Cu-low
K on April 26, 2005 at GT
Georgia Tech-PRC proposes an Industry-Academic
Workshop on Copper low-K. While the industry has introduced copper with
low-K, true low-K around 2.2-2.5 remains a challenge. PRC would like some
of its expertise to bring about a total System approach to Cu low-K with
focus on Electrical and Mechanical IC/package co-design. The research focus
would be in the following areas:
- New substrates with low TCE for low stress
- Multiple approaches
to interconnections
- Low-K characterization and adhesion
- Advanced assembly processes
to low-K
- Test vehicles and reliability assessment
For more information and registration details on the Workshop you may
visit the PRC web site at: http://www.prc.gatech.edu/events/culowk/2005/index.htm
(Contact Prof. Suresh Sitaraman: suresh.sitaraman@me.gatech.edu)
WOB (Wire on Bump) SIP Technology
PRC has developed a new approach
for memory chip stacking called Wire-on-Bumps (WOB) with lower cost,
better electrical properties and higher Si efficiency than conventional
wire bonding, interposer or Si through via technologies. The new WOB
technology is based on peripheral pad redistribution and formation of
solder bumps followed by straight and vertical wire bonding. The memory
chip stack by WOB can then be mounted on mother board by balls or wires,
with or without interposer for consumer or harsh applications.The WOB
technology is under development and PRC is looking for industry partners
to further envision this technology and its applications. (Contact Dr.
Chong Yoon: cyoon@ece.gatech.edu)
New Research Fellows join PRC
‘Lilly’ Jui-Yun Tsai has a PhD degree
in Chemical and Material Engineering from National Central University, Taiwan, in 2004. She will work on fine-pitch flip-chip assembly process
including reliability test, wire-on-bump (WOB) for 3-D packaging and
lead-free wafer bumping process at PRC. (jt05@ece.gatech.edu)
Baik-Woo Lee received his PhD degree in material science
and engineering from Seoul National University, Korea, in 2004 and
will work on embedded actives, wire-on-bump (WOB) for 3-D package stacking
and nanocomposite capacitor at PRC. (baikwoo@ece.gatech.edu)
Ege Engin was with the Fraunhofer Institute IZM from
2001 to 2004. He received his PhD from the University of Hannover, Germany
in 2004 and he will work in the areas of mixed-signal design, and electrical
modeling and characterization of IC packages. (engin@ece.gatech.edu)
Boyd Wiedenman received his B.S. in Chemistry from
Colorado State University in 1995. He has ten years of industry experience
with semiconductor fabrication process integration and MEMS process development,
most recently from Sandia National Laboratories, California. He is currently
a Research Engineer with the PRC at Georgia Institute of Technology working
with digital wiring and dielectrics, embedded passives, and process integration
for next generation system on packages (SOP) platforms. (bwiedenman@ece.gatech.edu)
Visiting Scholars to PRC
Dr. Yoshitaka Toyota from
Okayama University, Japan has joined the Epsilon Group at Georgia Tech
in 2005. He will work on optical interconnection on PCB, EMC design for
high-speed digital systems etc. (yoshitaka.toyota@ece.gatech.edu)
Workshops on Emerging Technologies
The Second International Workshop on Nano and Bio-Electronics
Packaging will be held March 22-23, 2005 at the Technology
Square Research Building, Georgia Tech. The Workshop will have 5 keynote
speakers and 6 technical sessions. The Conference Chairs are Prof. Rao
R. Tummala and Prof. Z L Wang. The Conference Coordinator is Dr. Swapan
Bhattacharya. (swapan@ece.gatech.edu)
PRC and IEEE-CPMT jointly sponsor the First
International Workshop on 3S (SOC • SIP • SOP) Electronics Technologies on
September 22 and 23, 2005 at the Global Learning and Conference Center,
Georgia Tech, Atlanta. Prof. Rao R. Tummala is the General Conference
Chair. Boyd Weidenman is the Program Coordinator (bwieden@ece.gatech.edu).
More details are also available at the PRC web site: www.prc.gatech.edu/3s
Infrastructure Partners
The PRC wishes to extend thanks to its infrastructure partner, BTU
International, for its support of the recently-installed Pyramax 98
belt reflow oven for use in eutectic and lead-free interconnect research
and test bed assembly efforts. (Contact Dean Sutter: dean.sutter@ee.gatech.edu)
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