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Events and Programs:
Professors Rao Tummala and Madhavan Swaminathan Meet with Indian Semiconductor Companies in Bangalore, India
 On Aug. 4th, 2008, Professors Rao Tummala and Madhavan Swaminathan (Microsystems Packaging Research Center, Georgia Tech) presented a seminar to about 30 Indian Semiconductor companies in Bangalore, India, hosted by ISA, Indian Semiconductor Association.
They proposed how India can become a global player in hardware electronics by focusing on 2nd Law of Electronics in contrast to the 1st Law every one else did. They highlighted three parts of an emerging paradigm—the Second Law Technology Paradigm, New Design, and Manufacturing Approaches.
Presentation Abstract
Since electronics continues to be one of the largest global industries, it has become the driving engine for science, engineering and manufacturing, leading to global prosperity for the parts of the world that invested and participated in it. India missed the opportunity to be a global electronics player over the last 50 years, except in software in recent years. A new opportunity appears on the horizon for India to be a global player this time around.
The first electronics wave, starting with the transistor, was largely due to Moore’s Law, or, the First Law of Electronics, and the associated hybrid approach to systems using hundreds of discrete components made of ceramics, organics, silicon, metals and alloys. The end of the era using this approach seems evident.
It appears that the timing is right for a Second Law of Electronics, which focuses on system integration, miniaturization, functionality and cost, rather than pushing CMOS for miniaturized nodes.
Georgia Tech has been a pioneer of this Second Law approach in which electronics system functionality is achieved by system miniaturization and the three dimensional packaging of integrated circuits, packages, components, interconnections, battery and thermal interfaces.
For further information, please contact the PRC at 404-894-9097 or prcinfo@ece.gatech.edu.
PRC Proposes Industry Consortium on Next Generation Flip-Chip with Advances in Substrate, Warpage Reduction, Interconnections and Assembly (NGFC)
Dramatic growth and advances in semiconductor technology have placed stringent requirements on flip-chip interconnects, substrate wiring, and via density. To achieve high reliability, high wiring and via density, and good assembly yield, there is a need to investigate novel interconnect methods, underfill materials, and cored and coreless substrate materials. In addition, substrate planarity and warpage must be tightly controlled to achieve dimensional stability which becomes even more critical as flexible core-less substrates gain momentum due to cost considerations. The Microsystems Packaging Research Center at Georgia Institute of Technology (PRC) proposes to create an Industry-Academia collaborative consortium to address interconnects, substrate warpage, and assembly challenges in terms of materials, processes and design considerations. The PRC is working on several innovative approaches that include novel interconnects, new underfills, substrate and dielectric materials and their processing, warpage prediction models, ECAD-MCAD integration tools, as well as guidelines for warpage reduction. The first open-to-all workshop of this consortium is planned for September 19, 2008 at Packaging Research Center, Georgia Tech USA.
Please contact nitesh@gatech.edu for more information reg the program and/or workshop.
Georgia Tech PRC’s Global Industry Collaborations
Industry interest in PRC continues to be strong and continues to grow. Many companies continue to show interest in existing, as well as new PRC initiatives. Within the past six months, many new companies have chosen to join and several other companies have either announced intent to join or fulfilled contractual/membership renewal obligations with the PRC. These groups of new and renewing companies include the names below bringing the total PRC industry support to 42 companies from around the world.
The PRC team extends renewed welcome and thanks to these companies and their representatives who continue to support our research efforts!
The companies listed below are currently affiliated with the PRC and represent project members, individual contracts, infrastructure partners, and consortia program (EMAP, MSDT, TIM, Base SOP) members. Many are involved in multiple memberships and contracts.
For further information, please contact the PRC at 404-894-9097 or prcinfo@ece.gatech.edu.
September 15-19, 2008 Industry Week at Georgia Tech Microsystems Packaging Research Center
September 15-19, 2008 will be the PRC’s week-long consortia development event. Included are well-established industry programs that are open only to the paying members, as well new programs that are open to all companies. The existing programs are: Mixed Signal Design & Tools (MSDT), Thermal Interface Materials (TIM), and Embedded Actives and Passives (EMAP).
Intended for new members are two new proposed industry consortia which will focus on: 1) ultra-miniaturized bio-electronics with System-on-Package technologies (BioSOP), and 2) next generation flipchip with advances in substrate, warpage reduction, interconnections, and assembly. Both workshops are free of charge and open to all interested industry representatives. Lunch will be provided.
For additional information on these and other PRC Industry Week programs, please see Industry Week At-A-Glance at http://www.prc.gatech.edu/events/glance.
Laboratories and Equipment:
PRC Expands Capabilities with Brewer Science’s “CON-TACT” Planarization Tool
 In partnership with the PRC, on an in-kind basis for membership in the PRC’s EMAP program, Brewer Science Corporation, based in Rolla, Missouri, U.S.A., has agreed to place a new $150,000 CON-TACT Planarization System in the PRC’s testbed laboratories. The system will be used in various PRC organic packaging research programs that focus on substrate surface planarization for ultra-fine pitch flipchip interconnects where targeted co-planarities are typically in the 0.5-1µm range and in silicon packaging research projects where the planarization of various levels in a stacked silicon die with through-silicon vias are needed. The tool is being considered as a low-cost alternative to the more expensive technology in use today.
For More Information on the CON-TACT Planarization System, please contact Jeremy McCutcheon, managing director, R&D Advanced Technologies, Brewer Science, 2401 Brewer Drive, Rolla, MO 65401, E-mail: jmccutcheon@brewerscience.com, Phone: 573-364-0444 x1379.
Computer Simulation Technology (CST) Donates Design Simulation Software
Computer Simulation Technology (CST) has donated design simulation software called “CST DESIGN STUDIO™'s”. Its open architecture enables the user to combine results from the best source available (simulation tool, analytical model, measurement results) in one user-friendly environment.
For more information on how CST can help with your needs contact Antonio.Ciccomancini@cst.com or Nadine.Graef@cst.com
Sigrity Licenses PRC for Power and Signal Integrity Analysis Software
Sigrity, a provider of software tools for power and signal integrity providing electrical analysis of integrated circuit (IC) packages and printed circuit boards (PCBs) provided a license for the use of the PRC Design team.
If you are interested in finding out more about Sigrity products, contact Bob Ellis, Eastern Regional Sales Manager, (781) 418-6349, Cell (978) 376-0229, bobellis@sigrity.com.
Innovations:
Flexible Polymer Optical Subassembly Demonstrated for Board-to-board Application in Servers and Routers
Professor Gee-Kung Chang and Dr. Daniel Guidotti demonstrated a flexible polymer optical subassembly for board-to-board application in servers and routers. The main features are a high-density electrically pluggable board interface, 10 Gb/s per channel, roll-to-roll mass producible, automatic parallel optical pre-alignment, field repair/upgrade capable, short reach (up to 1 m), power dissipation comparable or less than Cu over speed-distance, low cost (initial target $10/Gb/s).
For further information on this research, please refer to the following publications or contact Prof. Gee-Kung Chang (gkchang@ece.gatech.edu) or Daniel Guidotti (daniel.guidotti@ece.gatech.edu).
- Yin-Jung Chang, Daniel Guidotti, Lixi Wan, and Gee-Kung Chang, “Flexible polymer optical bus for inter-board optical interconnects,” LEOS Annual Meeting, Lake Buena Vista, FL, Oct. 24, 2007.
- Ying-Jung Chang, Daniel Guidotti and Gee-Kung Chang, “An anchor-board-based flexible optoelectronic harness for off-chip optical interconnects,” IEEE Photonics Technology Letters, Vol. 20, pp 839, 2008.
- Shu-Hao Fan, Daniel Guidotti, Claudio Estevez, Gee-Kung Chang and Daoquiang Daniel Lu, “Short-reach flexible optical interconnection using embedded edge-emitting lasers and edge-viewing detectors,” Proc. SPIE Vol. 6899, pp. 689905-1-11, 2008.
- Shu-Hao Fan, Daniel Guidotti, Hung-Chang Chien, and Gee-Kung Chang, “Compact polymeric four-wavelength multiplexers based on cascaded step-size MMI for 1G/10G hybrid TDM-PON applications,” Accepted for publication in Optics Express, 2008.
New Invention Disclosures
- Embedded TSV Chip Stack - Authors: Baik-Woo Lee, Venkatesh Sundaram, and Rao Tummala
- Power Transmission Lines for High-Speed Signaling - Authors: Ege Engin and Madhavan Swaminathan
For further information, please contact the PRC at 404-894-9097 or prcinfo@ece.gatech.edu.
Material Property Calculator
A confirmatory software license for the Material Property Calculator, developed by the PRC, was issued to PRC member, Samsung Techwin Company, Ltd.. The software is used to model mechanical reliability and was developed by Georgia Tech professor Suresh Sitaraman and PRC student, Luke McCaslin.
For further information, please contact the PRC at 404-894-9097 or prcinfo@ece.gatech.edu.
Awards:
 Regents' Professor, C. P. Wong, Receives Total Excellence in Electronics Manufacturing Award
C. P. Wong, Regents' Professor and the Charles Smithgall Institute Endowed chair, received the 2008 Total Excellence in Electronics Manufacturing (TEEM) Award by the Society of Manufacturing Engineers in recognition of his extraordinary dedication to setting new or higher standards of achievement in electronics manufacturing. He received this Award on June 1, 2008 in Detriot at the SME Annual meeting.
According to John Pan, PhD, 2008 TEEM selection committee chairman, "Dr. Wong has contributed significantly through both research and teaching to the fields of polymeric materials, materials reaction mechanism, IC packaging, in particular, hermetic equivalent plastic packaging processes, interfacial adhesions, PWB, SMT assembly and components reliability.”
Additional information
Students:
Recent Student Graduates
During the Fall 2007 and Spring 2008 semesters, the following students graduated who were enrolled in PRC courses, listed under their mentors:
Prof. Rao Tummala
Dhanya Athreya, Masters Degree in Electrical and Computer Engineering, Thesis: “Design, Fabrication and Measurement of Embedded Passives and Filters on Ultra-thin Organic Substrates” - Employed by Intel.
Gopal Jha, Masters Degree in Materials Science and Engineering, Thesis: “Copper To Copper Bonding by Nano Interfaces for Fine Pitch Interconnections and Thermal Applications” - Employed by Qualcomm.
Gaurav Mehrotra, Masters Degree in Materials Science and Engineering, Thesis: “Ultrathin Ultrafine-Pitch Chip-Package Interconnections for Embedded Chip Last Approach” - Employed by Intersil Corporation.
Prof. Suresh Sitaraman
Shashikant Hegde, Ph.D. in Mechanical Engineering, Thesis: “Investigation of Optical Loss Changes in Siloxane Polymer Waveguides during Thermal Curing and Aging” – Employed by Micron Technologies
Injoong Kim, Ph.D. in Mechanical Engineering, Thesis: “Development of a Knowledge Model for the Computer-Aided Design for Reliability of Electronic Packaging Systems” – Employed by LG Electronics
Lucas McCaslin, MS in Mechanical Engineering, “Thesis: “Methodology for Predicting Microelectronic Substrate Warpage Incorporating Copper Trace Pattern Characteristics” – Employed by NAC International
Krishna Tunga, Ph.D. in Mechanical Engineering, Thesis: “Study of Sn-Ag-Cu Alloy Reliability through Material Microstructure Evolution and Laser Moire Interferometry” – Employed by IBM Corporation
Prof. John Papapolymerou
Bo Pan, Ph.D. in Electrical and Computer Engineering, Thesis: “Development of Micromachined mm-Wave Modules for Next-generation Wireless Transceiver Front-ends" – Employed by Wionics, RealTek, California
Prof. Madhavan Swaminathan
Subramanian Lalgudi, Ph.D. in Electrical and Computer Engineering, Thesis: "Transient Simulation of Power-Supply Noise in Irregular On-Chip Power Distribution Networks using Latency Insertion Method". - Employed by Ansoft Corporation
Wansuk Yun, Ph.D. in Electrical and Computer Engineering – Employed by Broadcom Corporation.
For further information, please contact the PRC at 404-894-9097 or prcinfo@ece.gatech.edu.
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| Nithya Sankaran, Tapobrata Bandyopadhyay, and Gaurav Mehrotra |
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| Jin Liu and Yonghao Xiu |
IEEE-CPMT Student Chapter Booth at ECTC Conference
ECTC has been a primary vehicle for the Chapter students to get visibility externally of GT and GT typically has a strong presence. This year at ECTC 2008, GT presented 27 papers, had 11 student posters, this in addition to having a student booth for the 2nd consecutive year. Additionally, Mr. Tapobrata Bandyopadhyay has been announced as the winner of the 2008 IEEE-CPMT Ph.D. Student Fellowship.
June newsletter featuring IEEE-CPMT Student Chapter activities
Personnel:
PRC Promotes and Welcomes New Research Engineers
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| Venky Sundaram, Senior Research Engineer |
Consistent with its changing program contents, the PRC continues to offer an environment of ever-changing needs for staff research and administrative personnel.
The PRC extends a warm welcome to the following staff members who recently joined or will join the PRC shortly: Dr. Himani Sharma (embedded passives), and Drs. Daehyun Chung and Sung Hwan Min (design).
The PRC is also proud to announce the promotion of Mr. Venkatesh (Venky) Sundaram to Senior Research Engineer—a well deserved promotion for all his efforts associated with developing and engaging industry in the PRC’s organic packaging arena.
The entire PRC team wishes to extend its best wishes to former staff members who pursued new opportunities outside Georgia Tech, including: Dr. Chong Yoon, Dr. Ege Engin, and Dr. Andy Seo.
For further information, please contact the PRC at 404-894-9097 or prcinfo@ece.gatech.edu.
Two New Additions to the PRC Family
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| Aneesh Sundaram |
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| Syamala Sravani Pulugurtha |
Aneesh Sundaram, a baby boy, was born on Aug. 8, 2008 (8-8-08) weighing 6 lbs, 6 oz, at 9:05 p.m. to PRC Senior Research Engineer, Venky Sundaram, and his wife. Mother and baby are doing fine. Aneesh was named after a Hindu God.
Syamala Sravani Pulugurtha, newest daughter of Dr. Raj Pulugurtha, was born on Aug. 9, 2008 at 12:46 a.m.
While at the same hospital, Dr. Pulugurtha and Mr. Sundaram spent the first night staring through the nursery’s glass window watching their new babies.
Congratulations Raj and Venky on your new additions!
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