GIT2012

IEEE GIT2012 FINAL PROGRAM

WEDNESDAY, NOVEMBER 14, 2012

7:30 - 8:30	Breakfast and Registration
8:30 - 8:45	Welcome and Introductions
9:00 - 4:00	Plenary Keynote Session

Plenary Keynote Speakers

Session 1		Session 2
Subramanian Iyer IBM Co-Chair	William Chen ASE Co-Chair	Doug Yu TSMC Co-Chair	Sesh Remaswami AMAT Co-Chair
Suresh Ramalingham XILINX "Recent Advances in 2.5 D and 3D"		Joungho Kim KAIST "Silicon vs. Glass Interposer: A comparative study - bandwidth, I/O, power and noise"
Matt Nowak QUALCOMM "2.5D Interposers and 3D TSV DRAM stacking – what's next?"		Phil Garrou YOLE DEVELOPPEMENT "The interposers market: A 2012 update"
Rao Tummala GEORGIA TECH "Glass and silicon interposers and packages, 1st step in system scaling for Smart consumer systems"		Sitaram Arkalgud SEMATECH "Scaling 2.5/3D -- the next R&D Challenge"
Jon Greenwood GLOBAL FOUNDRIES "Collaborative R&D for enabling advanced packaging and supply chain solutions"		Peter Bocko CORNING "Glass as an enabling semiconductor packaging material: myths, potential and challenges"
Nagesh Vodharalli ALTERA "Needs, challenges and status in low-cost silicon interposers"

4:15 - 5:45	Plenary Panel Discussion: Silicon vs. Glass and Wafer vs. Panel
Plenary Panel Discussion Participants

Rao Tummala GEORGIA TECH Moderator	Subramanian Iyer IBM	Doug Yu TSMC	Suresh Ramalingham XILINX
Matt Nowak QUALCOMM	Jon Greenwood GLOBAL FOUNDRIES	Nagesh Vodharalli ALTERA	Joungho Kim KAIST
Sesh Ramaswami APPLIED MATERIALS	Phil Garrou YOLE DEVELOPPEMENT	Sitaram Arkalgud SEMATECH	Peter Bocko CORNING

THURSDAY, NOVEMBER 15, 2012

7:30 - 8:30	Breakfast and Registration
8:30 - 8:45	Welcome and Announcements
8:45 - 10:05	Electrical Modeling and Design Session Co-Chairs: Suresh Ramalingham, Xilinx; Madhavan Swaminathan, Georgia Tech

Electrical Modeling and Design Session Speakers

Session Keynote: Madhavan Swaminathan GEORGIA TECH "Power distribution methods for 3D I/O signaling"	Darryl Kostka CST "TSV and Silicon Interposer - 3D Numerical Modeling and Characterization"	Sooyong Kim APACHE DESIGN "Extraction and silumation of complex silicon interposer structures with measurement correlation"	Hiroyuki Honda STARC "Electrical modeling technique of silicon interposer for chip-package-board co-design"

10:35 - 12:00

Mechancial Modeling and Design Session Co-Chairs: Rajiv Dunne, TI; Suresh Sitaraman, Georgia Tech

Mechanical Modeling and Design Speakers

Session Keynote: Bucknell C. Webb IBM "Mechanical modeling and analysis for 3D design, handling and assembly" Abstract	Ahmer Syed AMKOR "Electromigration reliability of multi-scale 3D interconnects: from micro-bumps to BGA solder joints"	Suk-Kyu Ryu UNIVERSITY OF TEXAS "Thermomechanical characterization of TSV structures for 3D integration"	Suresh Sitaraman GEORGIA TECH "Reliability of 3D interconnects"

1:25 - 2:50

Silicon Interposes and Packages Session Co-Chairs: Nagesh Vodrahalli, Altera; Alan Huffman, RTI

Silicon Interposers and Packages Speakers

Session Keynote: Ming Li RAMBUS "Design and Manufacturing challenges for a 2.5D Silicon interposer with double side active die attachments"	Session Keynote: Yann Lamy CEA LETI "More-wires vs. more-than-wires"	Mathias Boettcher FRAUNHOFER, IZM "2.5D Interposer – An integral element of multi-functional 3D-systems"	Erik Vick RTI "Electrical demonstration of TSV and multi-level metallization technology for Silicon interposers"

3:20 - 4:50

Glass Interposers and Packages Session Co-Chairs: Venky Sundaram, Georgia Tech; Shintarou Takahashi, Asahi Glass

Glass Interposers and Packages Speakers

Session Keynote: Venky Sundaram GEORGIA TECH "Low-cost double-side ultra-Thin glass interposer and package"	Session Keynote: Nobuhiko Imajo ASAHI GLASS "Through Glass Vias (TGV) technology for larger interposer substrate"	Aric Shorey CORNING "Development of Through Glass Via (TGV) substrates for 3D-IC integration"	Tomotaka Katsura MITSUBISHI ELECTRIC "High-speed drilling through-holes in Borosilicate glass substrates by high-peak-power CO2 laser"

5:00 - 7:00	Academic Students and Industry Poster Session
Academic Session Poster Awards Committee
Sitaram Arkalgud William Chen Jon Greenwood Subramanian Iyer Joungho Kim Matt Nowak Sesh Ramaswami Suresh Ramalingham Suresh Sitaraman Madhavan Swaminathan Nagesh Vodharalli Doug Yu

			Industry Participants Atotech Bridge Semi IMEC IZM Fraunhofer National Key Lab Tamar Technology	University Participants Univ. of Alabama Georgia Tech Univ. of Maryland No. Carolina State U Peking University Univ. of Rabat TU Dresden
Rao Tummala GEORGIA TECH Co-Chair	Subramanian Iyer IBM Co-Chair	Saumya Gandhi GEORGIA TECH Co-Chair

FRIDAY, NOVEMBER 16, 2012

7:30 - 8:30	Breakfast and Registration
8:30 - 8:50	Welcome and Announcements
8:50 - 10:00	Chip and Board Level Interconnections Sessions Co-Chairs: Ron Huemoeller, Amkor; Sung Jin Kim, Georgia Tech

Chip and Board Level Interconnections Speakers

Session Keynote: Mark Gerber TEXAS INSTRUMENTS "Chip level interconnect enabling next generation devices"	Session Keynote: Sung Jin Kim GEORGIA TECH "Next generation PoP for bandwidth of  next generation Smart phones"	KS Choi ETRI "Novel Solder-on-Pad (SoP) material and process for low-cost interposers"

10:00 - 10:30	Student Poster Session Awards
10:30 - 12:00	MEMS and Passives Session Chair: Raj Pulugurtha, Georgia Tech and Farrokh Ayazi, Georgia Tech

MEMS and Passives Speakers

Session Keynote: Farrokh Ayazi GEORGIA TECH "Next gen MEMS challenges and MEMS packaging consortia to address these challenges"	Session Keynote: P.M. Raj GEORGIA TECH "3D IPAC: A new actives and passives concept for ultra-miniaturized functional modules"	Charles Sullivan DARTMOUTH "Nanogranular nagnetic materials for enhanced low-profile inductors"	Danny Xiao INFRAMAT "Fabrication of nanostructured magnetic thick films for microelectronic applications"

12:00 - 1:30

Lunch and Closing Remarks by Rao Tummala