Next-Generation Flip Chip:
Substrate, Warpage, Interconnects and Assembly (NGFC)

Dramatic growth and advances in semiconductor technology have placed stringent requirements on flip-chip interconnects, substrate wiring, and via density. To achieve high reliability, high wiring and via density, and good assembly yield, there is a need to investigate novel interconnect methods, underfill materials, and cored and coreless substrate materials. In addition, substrate planarity and warpage must be tightly controlled to achieve dimensional stability which becomes even more critical as flexible core-less substrates gain momentum due to cost considerations.

The Microsystems Packaging Research Center at Georgia Institute of Technology (PRC) proposes to create an Industry-Academia collaborative consortium to address the interconnects substrate warpage, and assembly challenges in terms of materials, processes and design considerations.

The PRC-GT is working on several innovative approaches that include novel interconnects, new underfills, substrate and dielectric materials and their processing, warpage prediction models, ECAD-MCAD integration tools, as well as guidelines for warpage reduction.

Novel Interconnects and Underfill

• Advanced UBM for electromigration
• Nano-composite solders for enhanced reliability
• Novel low stand-off and fine pitch underfill material and process

Organic Substrates

• Low and medium CTE substrates for  fine pitch flip-chip reliability
• Fine pitch wiring processes for sub-10µm lines/spaces and sub-25µm vias for area array fine pitch flip-chip interconnect
• Fine-pitch assembly with ultra-thin core and coreless substrates

Module and Substrate  Warpage: Modeling, Measurement and Control

• Design and Simulation
  • ECAD to MCAD – seamless analysis techniques
  • Trace layout and local substrate behavior
  • Core and coreless substrates with build-up layers – warpage prediction
• Metrology and Validation
  • Warpage measurement metrology
  • Core substrate warpage measurement
  • Coreless substrate warpage – gravitational effects
• Warpage Reduction and Targets
  • Processing conditions and warpage
  • Material selection and warpage
  • Trace layout and warpage

Who Should Attend
Research directors, senior engineers and managers from semiconductor, system, energy, biotech, automotive, defense and aerospace industries are invited to attend the exploratory workshop.

Registration

Event over. Registration closed.

Hotels & Accomodations

Visitor Travel Info

Contacts

Prof. Suresh Sitaraman, Suresh.sitaraman@me.gatech.edu, 404-894-3405
Prof.  Rao Tummala, rao.tummala@ee.gatech.edu, 404-894-9097
Mr. Nitesh Kumbhat, nitesh@gatech.edu, 404-385-0730

Agenda (Tentative)

Last update: September 18, 2008

Download agenda (PDF)

September 18 (Thursday), 2008

Registration and Coffee: 08:00 AM~08:30 AM, MaRC Atrium

08:30 AM~09:00 AM - Welcome and Objectives

Consortium and Program Objectives – Prof. Suresh Sitaraman
Introduction to PRC and its programs – Prof. Rao Tummala     

09:00 AM~09:40 AM - Current and Proposed Research

Novel UBM and Interconnects – Dr. Raj Pulugurtha
Next Generation Organic Substrates – Venky Sundaram

Coffee Break: 09:40 AM~10:00 AM

10:00 AM~11:00 AM - Current and Proposed Research

Design and Simulation of Module Warpage and Reduction Targets – Prof. Suresh Sitaraman
ECAD to MCAE Integration for Automated Warpage Simulation – Dr. Russell Peak
Novel Underfills – Prof. C. P. Wong

11:00 AM~11:45 AM - Consortium Development, Feedback and Wrap-up

IP Management and Membership Fee – Dean Sutter
Industry Feedback and Wrap-up – Prof. Suresh Sitaraman & Prof. Rao Tummala

Lunch: 11:45AM, MaRC Atrium