September 18-19, 2008

Microsystems Packaging Research Center
Manufacturing Research Center (MaRC) Building, Room 114
813 Ferst Drive, Atlanta, GA, Atlanta, Georgia U.S.A.

Map, Directions & Parking | Visitor Travel Info | Download Agenda (PDF)

Program intended for Industry Only.

A major bottleneck in the development of next generation packaging technologies is the design tools. Due to the integration of heterogeneous functions in a package, mixed signal design tools are necessary that are part of a design flow. The Packaging Research Center (PRC) at Georgia Institute of Technology has been one of the pioneers in this area, introducing tools that address the System-on-Package (SOP) technologies. Design of such highly integrated mixed-signal systems require new tools that, for example, take into consideration the increased interaction between the IC and package leading to system miniaturization. This workshop is targeted to discuss the electrical and mechanical issues arising in mixed signal design, leading to the development of mixed-signal design tools through the formation of a consortium of companies at PRC, which can provide solutions in this area.

Topics

• Design Flow
• Electrical Chip-Package Co-Design
• Signal and Power Integrity
• Design Tools for RF Packaging
• Electromagnetic Analysis
• Circuit Analysis Methods
• Design for Manufacturing
• Physical Design

Who Should Attend?

Scientists, engineers and managers from, semiconductors, package and electronic systems in automotive, mobile communications, defense and aerospace industries are invited to attend the workshop.

Registration

Hotels & Accomodations

Visitor Travel Info

Contacts

Prof. Rao Tummala
rao.tummala@ee.gatech.edu
404-894-9097

Prof. Madhavan Swaminathan
madhavan.swaminathan@ece.gatech.edu
404-894-3405

Agenda

September 18, 2008

1:30pm – 2:00pm                       Welcome and Overview – Prof. Madhavan Swaminathan

SESSION 1: EDA for Digital and Mixed Signal

2:00pm – 2:15pm                       Overview – Prof. Madhavan Swaminathan

2:15pm – 2:40pm                       MSDT 1: Power Ground Network Simulator and Optimizer

                                                Technical Presentation – Krishna Bharath (20 min)

                                                Q&A (5 min)     

2:40pm – 3:05pm                       MSDT 2: Design for Manufacturing Methods for SiP

                                                Technical Presentation – Ranjeeth Doppalapudi (20 min)

                                                Q&A (5 min)

3:05pm – 3:30pm                       MSDT 5: EBG Modeling and Synthesis

                                                Technical Presentation – Bernie Jord Yang (20 min)

                                                Q&A (5 min)

3:30pm – 3:45pm                       Break

3:45pm – 5:15pm           Demo (MSDT 1, 2 and 5)

5:15pm – 6:15pm                       Poster Session

6:30pm                         Dinner (Georgia Tech Hotel or elsewhere - TBD)

September 19, 2008

SESSION 2: EDA for RF

8:00am – 8:30am           Continental Breakfast

8:30am – 8:40am                       Overview – Prof. Madhavan Swaminathan

8:40am – 9:30am                       MSDT 3: Automated methods for the design of EP

                                                3.1: Technical Presentation – Narayanan T V (20 min)

                                                Q&A (5 min)

                                                3.2: Technical Presentation – Mohit Pathak & Prof. SungKyu Lim (20 mins.)

                                                Q&A (5 min)

9:30am – 9:55am                       MSDT 7: Parametric models of Linear 3D Electrical Interconnects and Packages (EIP)

                                                Technical Presentation – Prof. Stefano Grivet, U. of Torino (20 min)

                                                Q&A (5 min)

9:55am – 10:10am         Break

10:10am – 11:40am       Demo (MSDT 3 and 7)

SESSION 3: EDA for 3D Multiscale Integration

11:40am – 11:50am       Overview – Prof. Madhavan Swaminathan

11:50am – 12:15pm       MSDT 4: EM Simulator for Chip-Package Co-Design

                                    Technical Presentation – Myunghyun Ha (20 min)

                                    Q&A (5 min)

12:15pm – 12:40pm       MSDT 6: Modeling of Coupling in 3D Integration

                                    Student Presentation – KiJin Han (20 min)

                                    Q&A (5 min)

12:40pm – 1:30pm         Lunch

1:30pm – 2:30pm                       Demo (MSDT 4 and 6)           

SESSION 5: MSDT Phase 2

2:30pm – 3:30pm           Phase 2 Discussions

3:30pm – 3:45pm                       Break

SESSION 6: IAB Feedback

3:45pm – 4:45pm                       Closed door IAB – Lead: Dr. Jochen Reisinger (Infineon) and Dr. Karl Wagner (Epcos)

4:45pm – 5:30pm                       Industry Feedback

5:30pm – 6:00pm                       Wrap – Up

6:30pm                         Dinner (Georgia Tech Hotel or elsewhere – TBD)

Demos:

MSDT 1 (Krishna Bharath)

MSDT 2 (Ranjeeth Doppalapudi)

MSDT 3.1 (Narayanan T V)

MSDT 3.2 (Mohit Pathak)

MSDT 4 (Myunghyun Ha)

MSDT 5 (Bernie Jord Yang)

MSDT 6 (KiJin Han)

MSDT 7 (Prof. Stefano Grivet Talocia)

Demos will provide details on Input/Output/Interface Formats and will apply the tool to several examples discussed in the presentation

MSDT Posters:

MSDT 1 (Krishna Bharath)

MSDT 2 (Ranjeeth Doppalapudi)

MSDT 3.1 (Narayanan T V)

MSDT 3.2 (Mohit Pathak)

MSDT 4 (Myunghyun Ha)

MSDT 5 (Bernie Jord Yang)

MSDT 6 (KiJin Han)

MSDT 7 (Prof. Stefano Grivet)

Whole program (Prof. Madhavan Swaminathan and Dr. Daehyun Chung)

Non-MSDT Posters:

RF / Mixed-Signal (Nevin Altunyurt, Abhilash Goyal, Eddy SeungHyun Hwang, Suzanna Huh, Dr. Daehyun Chung)

            3 posters

Digital Integration (Aswani Kurra, Vishal Laddha, Nithya Sankaran, Tapobrata Bandyopadhyay, Rishiraj Bheda, Jianyong Xie, Sukruth Pattanagiri, Dr. Daehyun Chung)

            3 posters