CALL FOR TITLES

Call for titles is requested for Interposer Technology in the areas of:

* Electrical Design
* Mechanical Design
* Interposer Technologies
* Interconnections

Markets and Applications
* Consumer and Mobile
* High Performance Computing
* Automotive and Harsh Environment
* Medical
* Defense

Manufacturing and Infrastructure
* Design Tools
* Materials and Processes
* Integrators
* Test

Deadline
September 1, 2011

Email to:
karen.may@ece.gatech.edu

IMPORTANT DEADLINES
Call for Titles:
September 1, 2011

Abstract Submission:
October 15, 2011

Early Registration:
October 15, 2011

Preliminary Technical Program Released:
October 15, 2011

FOR MORE INFORMATION
Please contact: karen.may@ece.gatech.edu

The Global Interposer Technology Workshop (GIT)

Interposers are becoming highly strategic for applications ranging from mobile products that require miniaturization, convergent systems with heterogeneous devices and high performance systems that require ultra-high I/O density and ultra short interconnections. The organic packages that are currently used are seen as reaching limits in I/Os thus requiring new interposer technologies.

3D ICs with TSV are being widely developed around the world for the same three reasons: for heterogeneous integration of ICs, improved electrical performance and for miniaturization of modules and systems. But these benefits come at very high cost and with significant disruption in wafer fabs. Additionally, the 3D stack approach presents major technical and manufacturing challenges that include testability and yield, scalability, along with thermal and standardized IC interface challenges.

Industry is exploring a variety of silicon and glass interposers that include an interposer alternative called 2.5 in the short term. Georgia Tech PRC is proposing a 3D interposer approach, as a better alternative, made of either low-cost ultra-thin polycrystalline silicon or low-cost ultra-thin glass, not only in 200-300mm wafer form but also in large, 450-700mm panel form. Such an interposer is identical to one of the 3D ICs in the 3D stack with regards to through-via interconnection length and interconnect density, and thus behaves just like a 3D IC stack with TSV.

The GIT Workshop is intended to compare and contrast the wide variety of interposer approaches being developed as well as promote and disseminate revolutionary and evolutionary advances in emerging silicon, glass and other interposer technologies, by bringing together academic and industry researchers, technology developers, users and manufacturers from around the world. Such a technology is seen as not only as packaging of ICs and 3D ICs but also act as a better alternative to 3D ICs with TSV and providing a path for future systems.

Workshop Topics Include:

• Electrical Modeling and Design
• Mechanical Modeling and Design
• Interposer Technologies: Silicon, Glass and Others
• Chip and Board Level Interconnections
• Applications and Markets
• Electrical Modeling and Design
• Manufacturing Infrastructure
• Electrical Modeling and Design
• Student Poster Session from Participating Universities