Jump to Specific 3DASSM Topics

Read Advanced Packaging (3/08) article, "The 3DASSM Consortium: An Industry/Academia Collaboration"

Ceramic substrates were the basis of high performance IC packages until 1990. For cost and performance reasons, organic substrates have taken over since then. However, organic substrates seem to have reached their limits in wiring density, cost and thermo-mechanical performance such as warpage and thermal management. Recent advances in Si wafer as the substrate with TSV, replacing flipchip and wirebond, with embedded thin film components, in addition to its outstanding intrinsic thermal properties such as CTE and thermal conductivity, may allow part or the entire system to be made of silicon. This can be referred to as silicon package replacing organic package. There is yet another concept to silicon systems that can be referred to as seamless integration of IC with its front end and back end as well as thin film fanout wiring that is typically done with organic packages. All these concepts can be envisioned to lead to an all silicon system—Si for ICs, packages and boards. Silicon, however, presents several challenges to achieve this vision, such as its electrically conducting properties, high fabrication cost and reduced mechanical strength.

The Microsystems Packaging Research Center (PRC) at the Georgia Institute of Technology (Atlanta, GA, USA), in partnership with Fraunhofer IZM (Berlin, Germany) and Korea Advanced Institute of Science and Technology (KAIST) (Daejeon, South Korea) will launch a global industry consortium titled 3D All Silicon System Module (3D-ASSM) in October, 2008.  This consortium will explore and develop Si as the IC and system technology by assessing system level benefits, identifying the challenges of Si based systems, and by executing a focused cross-disciplinary research to address the challenges and exploit the advantages of such systems.  The objectives will include system miniaturization, component integration, superior electrical and thermal performance, greater reliability, hetero-integration of components, reduced form factor, and low cost process innovations. 

A three phase execution strategy is envisioned for this program.  In the first phase, the focus will be on key building block technologies in five thrust areas: 1) Electrical and thermal design and test.  2) Multilayer Si substrate.  3) Low cost TSV.  4) Embedded thin film actives and passives.  5) IC to Si package and to board interconnections.  Approximately 20 projects have been proposed across these five thrust areas.  At the end of the first phase, some technologies from these thrust areas will be integrated to demonstrate an advanced Si package such as a BGA as shown in Figure 1.  The next phase will continue to enhance the building block technologies that were executed in the first phase including continuation of some projects or launching entirely new projects.  The second phase will also deliver an integration which will be a more advanced and highly integrated Si module incorporating a majority of the various building block technologies developed in the first phase.  Finally, the third and final phase will achieve a complete all Si system.

Prior to the launch of this global consortium, there will be four workshops held throughout the world to introduce the program to potential industrial partners.  The first workshop was held on the campus of GeorgiaTech (Atlanta, GA) on March 11-12, 2008.  There was a lot of interest with over 80 participants from 45 organizations attending this event.  The workshop was highly interactive and useful in the shaping of the program.  The general strategy of the program, as well as, first phase project details was shared during this first workshop.  The next workshop will be held in May 5-6, 2008 in Berlin, Germany, where a revised set of projects and integration plans will be discussed.  Subsequent workshops will be held in Japan on July 9, 2008 and Korea on July 11, 2008 prior to the launch of the consortium in fall 2008.

For more information on this consortium please contact Dr. Ritwik Chatterjee (email: ritwik@ece.gatech.edu or phone: 1-404-385-7302).

Topics

(A) 3D All Silicon System Module Design

• Signal  & power integrity & EMI
• Inter-stack coupling, TSV shielding
• RF/analog circuit and low power Designs
• Yield and test issues, Embedded BIST in Si substrate

(B) Si Substrate with Multilayer Wiring and Shielded TSV

• High density, fine pitch multilayer build up
• Si Core with optimized TSV materials & processes

(C)  Low Cost TSV

• Lower cost TSV formation  filling, and reliability
• Bonding and assembly  of 3D stacks

(D) Thin Film Active and Passive Components

• Ultra high Q RF inductors, High k, high µ materials
• Miniaturized High Efficiency Silicon Antennas
• Reconfigurable micro-antenna arrays in 3D wafer RDL
• Low loss and high K RF capacitors
• Horizontal and vertical EBG structures
• Embedded and transferable actives

(E) IC to Si Substrate-Board Interconnections and Reliability

• Low temperature Cu-Cu & Cu-Sn bonding
• Reactive thin film, metal-based bonding
• Advanced Open end CNT Interconnections
• Wafer level underfills for adhesion, stress relief & gap fill
• Flex SMT interconnections between Si substrate - PWB Board
• Interfaces, adhesion, and reliability
• Solder filled adhesive interconnect

(F) Advanced Thermal Solutions

• Modular heat spreaders
• Liquid cooling solutions for 3D systems
• System level thermal modeling for 3D systems design

Who Should Attend
Research directors, senior engineers and managers from semiconductor, system, energy, biotech, automotive, defense and aerospace industries are invited to attend the exploratory workshops in U.S., Europe and Asia.

Registration

Program intended only for INDUSTRY ONLY.

Hotels & Accommodations

Visitor Travel Info

Contacts

Dr. Ritwik Chatterjee (PRC), ritwik@ece.gatech.edu
Prof. Rao Tummala (PRC), rao.tummala@ee.gatech.edu
Prof. Herbert Reichl (IZM), Herbert.Reichl2@izm.fraunhofer.de
Rolf Aschenbrenner (IZM), aschenbr@izm.fhg.de
Prof. Joungho Kim (KAIST), joungho@ee.kaist.ac.kr

Agenda

3DASSM Project Selection and Supply Chain Workshop (October 28-29, 2008)

Program Selection Workshop (Tues., October 28, 2008)

8–9 AM:                    Registration

9–9:30 AM:               Welcome: Goals of the Workshop - Co-Chairs: Prof. Rao Tummala, Prof. Reichl, Prof. Kim

9:30-10:30 AM:          Proposed Initial Program - Co-Chairs: Prof. Rao Tummala, Prof. Reichl, Prof. Kim

10:30–11:00 AM:       Break

11:00–12:00 AM:        Industry Discussion

12-1:30 PM                 Lunch

Beyond 3D Supply Chain (SC) Partnership Workshop

1:30–2:30 PM:          Industry Feedback and Revised Proposal

2:30–3:30 PM:          Initial Technical Program - Co-Chairs:  Rolf Aschenberenner, Ritwik Chatterjee

3:30-3:45 PM:         Coffee

3:45–4:45 PM:         The Role of Supply Chain (SC) in 3DASSM

Dean Sutter
Prof. Michael Toepper

4:45–5:15 PM:         Supply Chain Expectations – An Industry Perspective

Invited Speaker

5:15–5:45 PM:            Invited SC Industry Speaker #1

5:45 – 6:15 PM:         Invited SC Industry Speaker #2

Beyond 3D Supply Chain (SC) Partnership Workshop (cont.) (Wednesday, October 29, 2008)

8:30 - 10 AM:          Finalize the Technical Program

10-10:30 AM            Coffee

10:30-12 PM:            Finalize Supply Chain Program

Program intended only for INDUSTRY ONLY.