3D All Silicon System Module (3DASSM) Consortium Workshop - Berlin, Germany

3D All Silicon System Module (3DASSM)
Project Selection and Supply Chain Workshop

October 28-29, 2008

REGISTRATION CLOSED
Program intended only for INDUSTRY ONLY.

CURRENT REGISTRANTS
ALLVIA, ATMI, DuPont, Entrepix, EV Group, Henkel Corporation, Ibiden USA, LSI Corporation, PVA TePla AG, Rogers Corporation, Semitool, Solid State Equipment Corporation, Taiyo America, Xradia

What is 3DASSM, Why, and How it Differs from 3D IC Programs?

Georgia Tech, Fraunhofer IZM (Germany) and KAIST (Korea) are proposing a global industry-academia consortium called 3D All Silicon System Module (3D-ASSM) which will focus on miniaturization of the entire electronic system using Si for ICs, packages, and boards. This approach is expected to result in high system performance at low cost and high reliability.

We expect to achieve this goal by exploring and developing interdisciplinary fundamental research in design and test, Si package replacing organic package, low cost TSV and stack bonding, thin film embedded active and passive components, and system interconnections. In addition, the consortium integrates the above fundamental research into useful test vehicles to demonstrate the commercial feasibility of cost effective 3D structures, silicon packages and all silicon modules with seamless integration of ICs with their FEOL and BEOL as well as with package wiring. A total of 20 plus projects are proposed in these areas.

How 3DASSM Differs from Other 3D Industry Programs

This program differs from other consortia and industry programs in several ways:

The 3DASSM starts with the current industry problem, the high cost and low reliability of TSV and stack-bonding. Here we propose several fundamental research projects to address cost and reliability, such as new fabrication methods for low cost and high density TSVs, new structures that improve thermo-mechanical reliability, novel low cost solder and adhesive stack bonding methods. In addition, this research will culminate in a 3D stack bonding test vehicle and a Si package test vehicle to demonstrate the improved performance, reliability, and manufacturability of the technologies developed.
3DASSM goes beyond current 3D programs to demonstrate double sided silicon package replacing organic package enabled by low cost TSV in a seamless integration. This test vehicle will address such shortcomings of organic package as wiring and I/Os, thermal performance, warpage, and cost.
The 3DASSM leads to next generation of wafer level packaging. This is referred to as Wafer System module in the 3DASSM. In this approach, ICs with both FEOL and BEOL are integrated with seamless integration of package wiring and cost effective thin embedded components on both sides of wafer enabled by TSV and 3D interconnections.

The ultimate goal is to design, demonstrate and commercialize a highly integrated all silicon system module (ASSM). The 3D-ASSM, therefore, is a global industry-Academia consortium on a global topic with potential to become a disruptive and revolutionary silicon module technology in the near term and a systems technology in the long term.

Membership Categories and Fees

In an effort to introduce this program to industry leaders such as yourself, we have held workshops in the USA (Atlanta), Europe (Berlin), and Asia (Tokyo and Seoul), with over 300 industry participants who provided very strong positive response and feedback to the proposed program.

There are three ways for companies to join this program:

Full Membership (Fundamental Research): $100K per year
Full Membership ( Integration plus Fundamental Research): $100K + $50K per test vehicle
Supply Chain Membership: Development of R&D and manufacturing infrastructure for materials, process and design tools: $50K per year

Benefits Companies Can Expect

Short Term Benefits: In the first two years, companies can benefit by applying to their needs from building block technologies as well as from integration and prototype research in low-cost TSV, 3D stack bonding and silicon package replacing organic package.

Mid Term Benefits: In the next two years, further advances in building block technologies as well as in integration and prototype research, leading to seamless integration of Silicon ICs and packages into a single monolithic silicon module with TSV, 3D stack bonding, advanced and lower cost embedded thin film components and silicon package to board interconnections will be pursued.

Long Term Benefits: The long term vision of 3DASSM is planned in the third phase. The second benefit that companies can expect to receive has to do with the expertise and facilities of the consortium members. Fraunhofer IZM, Georgia Tech PRC and KAIST are among the most well known academic organizations in the world, with the best facilities to carry out the proposed research.

Investment Benefit: Another benefit is the leveraging of company membership funds by a factor of about 20X. The consortium proposes to carry out more than 20 fundamental research projects, each at a cost of $125-150K per year and four integration projects at a cost of about $2 M per year. This adds up to approximately $5 M per year. The membership fee proposed for each company will be a factor of 20-30X less than this total investment.

Comparison of Other 3D-Centric Programs with 3DASSM

Comparison between 3DASSM and other 3D Industry Programs

	3D IC-Centric Programs	3DASSM
Electrical Design and Test	The 3D system-on-chip design research focuses on the development and demonstration of the IP and tools necessary for designing in three dimensions.	Focus is beyond 3D, starting with low cost 3D. Includes electrical design and test of TSV, 3D stack, SIP and BGA package and wafer system module. Research focuses on low signal switching noise, novel equalization methods, and EDA tools for electrical and thermal co-design.
TSV	This is an IC-centric program with focus on CMOS-compatible via first TSV approach focusing on low cost and high reliability.	Focus is on low cost, high density, and thermo-mechanical reliability. The research includes electrical design, mechanical design, low cost materials and processes, and novel geometries.
Stack Bonding	3D system-on-chip: post-passivation die-to-wafer or wafer-to-wafer low temperature bonding and chip embedding techniques using dielectric, adhesive, and metal based interconnections.	Focus is on die-to-wafer and wafer-to-wafer using novel low cost, thin, low temperature and fine pitch adhesive and metal-based interconnections for high density and high reliability.
Si Package for SiP and BGA	Si interposer with varying set of wafer level technologies.	Focus is on double-sided Si substrate enabled by TSV, replacing current organic SIP and Processor substrates with superior I/Os, wiring, planarity, thermal and electrical performance, reliability, and cost.
Embedded Thin Film Components	Embedded Si compatible thin embedded components.	Focus is on ultra thin micro-to-nano scale embedded actives and passive components with better properties at lower cost than has been achieved in Si and organic substrates.
System Interconnections	Fine pitch IC to substrate/interposerinterconnections.	Focus is on solving the mismatch challenge between Si package and organic Board by a variety of rigid and compliant interconnections.
Wafer System Module	Wafer level packaging focus.	Focus is on wafer level packaging with seamless integration of FEOL, BEOL, packaging wiring, interconnections and embedded components leading, ultimately, to All Si System.
Full IP to Companies	Yes	Yes
IDM and OEM Companies	Yes	Yes
Supply Chain (Tools and Materials)	Supply chain companies for TSV and stack bond tools and materials.	Full set of supply chain system companies from TSV to Package to Systems and from raw materials, engineered materials, large area materials, substrates, components, packages, process, and design tools.
Annual Fee	Very high.	Full Membership: ~$150 K Supply Chain Membership: $50K

Proposed Technical Content of 3D-ASSM Consortium

3D STACKING WITH TSV	TSV ENABLED SI INTERPOSER	WAFER SYSTEM MODULE

ELECTRICAL DESIGN OF TSV & 3D STACKS	ELECTRICAL DESIGN & TEST	ELECTRICAL DESIGN & TEST
Electrical and Thermal CAD (A-1)
	Design and optimization of power delivery networks for zero SSN (A2)
Hybrid equalization methods for high speed in 3D-ASSM (A-3)		Hybrid equalization methods for high speed in 3D-ASSM (A-3)
	Low Cost Test (A-4)
Design of TSV, High speed interconnects and vertical shielding (A-5)
LOWER COST TSV FABRICATION	LOW COST TSV AND MULTILAYER WIRING	WAFER LEVEL PACKAGE WIRING WITH TSV
	Advanced Dielectrics (B-1)
	Advanced conductors by Templating, Printing, and Additive Plating (B-2)
		Thin wafer level encapsulant (B-3)
Advanced coaxial TSV materials, processes and reliability (C-1)		Advanced coaxial TSV materials, processes and reliability (C-1)
	Low stress TSV (C-2)
Limits of TSV (C-3)		Limits of TSV (C-3)
	Advanced Printed TSV fill (C-4)
		Adhesive interconnections (C-5)
3D STACK BONDING & PASSIVE ISOLATION	EMBEDDED PASSIVES & ACTIVES	EMBEDDED PASSIVES
Adhesive interconnections (C-5)
Solder and non-solder based TSV metallic bonding (C-6)
	3D Antenna Arrays Modules for 60 GHz (D-1)
Ferroic layers for noise suppression through TSV and noise isolations (D-2)		Ferroic layers for noise suppression through TSV and noise isolations (D-2)
	Advanced embedding of stacked ICs in Si core (D-3)
	Re-configured organic flex layer with embedded active devices (ReCoFeD) (D-4)
	2nd LEVEL INTERCONNECT TO PWB	SI TO PWB DIRECT CHIP ATTACH
	Compliant 2nd level pillar interconnects (E-1)
	Compliant buildup dielectric for improved substrate to MB reliability (E-2)
	Compliant 2nd level with ball on TSV (E-3)
Reactive bonding based interconnects (E-4)

Agenda

3DASSM Project Selection and Supply Chain Workshop
(October 28-29, 2008)

Program Selection Workshop
Tuesday, October 28, 2008

8–9 AM: Registration and Continental Breakfast

9–9:30 AM: Welcome: Goals of the Workshop
Co-Chairs: Prof. Rao Tummala, Prof. Reichl, Prof. Kim

9:30–11:30 AM: Brief Fundamental Project Descriptions [More time here]

11:30–11:45 AM: Break

11:45 – 12:30 PM: Brief Test Vehicle Project Descriptions [Change this – more time]

12:30-1:30 PM: Lunch

1:30-2 PM: Proposed Initial Program
Co-Chairs: Prof. Rao Tummala, Prof. Reichl, Prof. Kim

2–3:30 PM: Company by company feedback and two projects by each
Co-Chairs: Rao Tummala, Herbert Reichl

3:30-3:50 PM: Coffee

3:50 – 5:00 PM: Preliminary Technical Program

6 PM: Dinner

Beyond 3D Supply Chain (SC) Partnership Workshop (cont.)
Wednesday, October 29, 2008

8:00-8:30 AM: Coffee

8:30 – 9:00 AM: Strategy for Supply Chain involvement in Test Vehicle Research - Venky Sundaram

9:00 – 9:15 AM: The Critical Elements of Supply Chain (SC) in 3D ASSM - Dean Sutter

9:15 – 9:30 AM: PRC Experience with Supply Chain - Dean Sutter

9:30 – 10 AM: Industry speaker: Role of the supply chain - Invited Speaker

10 – 10:20AM: Supply Chain company 1

10:20 – 10:40 AM: Supply Chain company 2

10:40-11:10 AM: Coffee

11:10 – 11:30 AM: Supply Chain company 3

11:30 – 11:50 AM: Supply Chain company 4

11:50 – 12:10 PM: Supply Chain company 5

12:10 – 1:20 PM: Lunch

1:20 – 1:40 PM: Supply Chain company 6

1:40 – 2 PM: Supply Chain company 7

2 – 2:20 PM: Supply Chain company 8

2:20 – 2:40 PM: Supply Chain company 9

2:40 – 3 PM: Supply Chain company 10

3 – 3:30 PM: Coffee

3:30 – 4:30 PM: Discussion and Finalize Supply Chain Program

Who Should Attend
Research directors, senior engineers and managers from semiconductor, system, energy, biotech, automotive, defense and aerospace industries are invited to attend the exploratory workshops in U.S., Europe and Asia.

Registration

REGISTRATION CLOSED
Program intended only for INDUSTRY ONLY.

Hotels & Accommodations

Visitor Travel Info

Contacts

Dr. Ritwik Chatterjee (PRC), ritwik@ece.gatech.edu, Phone: (404) 385-7302

Prof. Rao Tummala (PRC), rao.tummala@ee.gatech.edu

Prof. Herbert Reichl (IZM), Herbert.Reichl2@izm.fraunhofer.de

Rolf Aschenbrenner (IZM), aschenbr@izm.fhg.de

Prof. Joungho Kim (KAIST), joungho@ee.kaist.ac.kr

General Contact Information

PHONE: 404-894-9097
FAX: 404-894-3842
E-MAIL: prcinfo@ece.gatech.edu

POSTAL ADDRESS:
Microsystems Packaging Research Center
813 Ferst Street, Room 351
Atlanta, GA 30332-0560


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