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Next-Generation Flip Chip Interconnections and Substrates (NGFCS) for Emerging Cu-Low K Devices
An Industry-Academia Consortium in Partnership with IMEC-Belgium
Leaders: Profs. Rao Tummala, GT ECE & MSE (lead), M. Swaminathan, CP Wong and S. Sitaraman; Dr. Eric Beyne, IMEC
Launch Date: Spring 2008
Presentations from IMEC-Belgium Workshop | May 4, 2007 Workshop Agenda
Note: A white paper will be sent to companies in November 2007.
Contact: Dr. Raj Pulugurtha, raj@ece.gatech.edu
Focus: The Packaging Research Center at Georgia Tech (GT-PRC)–Atlanta, in partnership with IMEC-Belgium proposes to launch an industry consortium to investigate a total Interconnect and assembly solution for flicpchip packaging of next-generation ultra low k-Cu and other devices. The consortium proposes to go beyond traditional flip chip interconnections by providing a total system-level solution based on novel concepts in: 1) Electrical modeling, Design and Characterization 2) Low stress Interconnection and Assembly Materials and Processes 3) Advanced multilayer, fine pitch organic substrates with low to medium TCE and 4) Thermo-mechanical Modeling and design for reliability.
Proposed Projects
- Electrical Design Ultra fine pitch and Low stress Substrate: Materials & Processes
- Cu-lowk IC UBM and Barrier: Materials and Processes
- Thermo mechanical design
- Underfill Materials and Processes
- New Interconnection and Assembly Approaches: Materials and Processes
Participating Companies
- To be listed soon