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3D Silicon SOP (3DSiSOP )
An Industry-Academia Consortium

Leaders: Dr. Mahadevan Iyer

Goal: Si-based, Ultra Miniaturized Digital & Bio convergence

Launch Date: Spring 2008

Contact: Dr. Mahadevan Iyer, mahadevan.iyer@ece.gatech.edu

Research Tasks

1. Si SOP Design
   • Signal & power distribution
   • EMI shielding
   • Thermomechanical design
2. Low-cost Embedded Thin Film Components with Enhanced Properties
   • Ultra high Q inductors
   • High k, high µ materials
   • Embedded antennas and switches
   • RLC integration with better properties than on Si
3. Interconnections and Bonding
   • High aspect ratio TSV interconnects
   • Non-collapsible Cu-based bonds
   • Metallic bumpless and pillarless bonding
   • Reactive thin film, nano metal-based bonding
4. Si 3D Substrate and Board Fabrication
   • Multilevel ultra fine routing structures
   • Silicon based cooling solutions
   • Isolation of Si substrate and TSV
   • High density build up with ultra-thin silicon TSV
   • Embedded die and module integration
   • New concepts in 3D stacking processes

Participating Companies

• To be listed soon