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3D All Silicon Systems Module (3DASSM)
An Industry-Academia Consortium

 

Leaders: Ritwik Chatterjee, Profs. Rao Tummala, Madhavan Swaminathan, C. P. Wong, Suresh Sitaraman

Goal: Si-based, Ultra Miniaturized Digital & RF Convergence

Launch Date: June 1, 2009

Companies Expressing Interest: ALLVIA, Asahi Kasei EMD, ASE, ATMI, Bosch, DuPont, Entrepix, EVG, Fujikura, Henkel, Ibiden, LSI, NXP, Qualcomm, Rogers Corporation, Semitool, Solid State Equipment Corporation, STMicro, Taiyo Ink, Toyobo, and Xradia

Contact: Dr. Ritwik Chatterjee, ritwik.chatterjee@ece.gatech.edu

Focus: 3D All Silicon System Module (3D ASSM) Research - A Disruptive Technical Approach to Highly-Miniaturized and Ultra-Functional Packages and Systems

The long term vision of 3D All Silicon Systems Module (3D ASSM) is to go beyond 3D ICs to miniaturize the entire electronic or bio-electronic system using silicon or lower cost alternatives to Si, for ICs, packages and boards. This is envisioned to be accomplished by gradual miniaturization of all system components such as active and passive components, IC packages, modules, system boards, system interconnections, thermal structures and heat sinks, power supplies, and external connections.

The electronics technology focus to date has been to miniaturize ICs by advanced lithography technologies, which is expected to continue to 32 nm node and perhaps, beyond. However, because of the increasing cost and performance bottlenecks beyond 32 nm, the industry began to look at alternatives. This led to the current focus of   thinned and stacked 3D ICs, initially by wire-bond, later by flip-chip and most recently by Through-Silicon-Via (TSV).  But, while the 3D ICs is a major paradigm shift and the impact of 3D ICs is profound, they constitute a very small part of the system and their benefits are often lost in size, cost or electrical performance at system level. This is the first rationale for 3D ASSM.
Packaging technology advances have been at IC packaging level and at systems packaging level. Since the goodness of the IC is unknown until it is packaged, a variety of bulky IC packages such as QFP, QFN, BGA, CSP, etc., have been developed, often adding cost, size, reliability and performance penalties. The other reason for these packages is to interconnect these and other components to system boards which are even more bulky, more expensive, less reliable and low in performance. This is the second rationale for the proposed 3D ASSM.

The IC packaging started with ceramics in 1960s. When they became costly, bulky and low in performance, they were replaced by organic packages in 1980s. The organic packages are now reaching their limits in lithography and power dissipation, in addition to being high cost. Wafer level IC packaging, on the other hand, has been limited to low I/Os. This is the third rationale for 3D ASSM.

The 3D ASSM proposes to overcome the shortcomings of the above current approaches by addressing six major barriers.

1. Electrical Design for performance and functionality and thermo-mechanical design for reliability
2. Ultra-low cost through package vias (TPV) materials and processes in Si or its alternatives
3. Low-cost and ultra-high density double-sided wiring and dielectrics
4. Thin film nano-component materials and processes with better properties and lower cost than achieved before in Si
5. Interposer to PWB Interconnection reliability addressing the huge mismatch between Si of TCE of 3PPM and PWB of 17PPM
6. Thermal management addressing the miniaturization-driven system level heat flux

3D Systems Strategy: Si-Interposer and Wafer System Module to All 3D Silicon Systems

The proposed research strategy consists of two main approaches to realize the above vision. The first approach addresses the shortcomings of organic packages. This is proposed to be achieved by development of cost-effective silicon or alternative interposer. The proposed Si or alternate core Interposer addresses the shortcomings of previous reported Si interposers by IBM, Bell Labs and Toshiba in two ways: 1) lower cost achieved by larger area of panel processing as well as lower cost materials and processes, and 2) higher performance achieved by TSV/TPV.  

The second approach takes wafer level packaging to the next step by the proposed Wafer System Module (WSM) with Seamless integration of CMOS IC with its FEOL, BEOL, and package and system components enabled by low cost TSV at wafer level. In this approach, unlike in the past by wafer level packaging, the new wafer systems integration is enhanced by low cost TSV for double side integration, low cost wiring and dielectrics, nano-scale miniaturized system components including thermal interfaces, system interconnections and in the long run nano-scale batteries. The above two approaches are consistent with Yole market report for 3-D WLP with TSV and 3-D Si-interposer with TSV. Yole reports that the combined market for these two to be about 18% of the total TSV market in the near future. 

Benefits of 3DASSM System Technologies::

• Improved Electrical Performance: Miniaturization of Silicon-based system with TSV/TPV and advanced materials and shortest interconnections are expected to lead to higher performance.
• Improved wiring and I/O Unlike ceramic and organic packages, silicon interposers and wafer level packages have already been demonstrated with sub-micron wiring at less than 20 micron pitch. The proposed research aims to achieve these with better and lower cost materials and processes.
• Better Mechanical performance: Si technology provides advantages in planarity and warpage at substrate level because of its higher modulus and at module level because of its Si-matched   TCE.
• Improved Thermal performance: Si has a thermal conductivity that is ~2 orders of magnitude higher than the present organic materials technologies.  This property of Si may be especially important for better heat spreading in high performance applications.
• Improved Thermo-mechanical reliability: Since Si is used for both ICs and packages in the short term and systems in the long run, with the same TCE for all, the interconnection reliability, as well as ultra-low-k BEOL structure reliability are greatly improved.
• Lower Cost per Function:  Cost advantages are due to large area processing and miniaturized area of the system. In addition, lower cost materials, processes, lower cost facilities and high throughput tools are expected to contribute further.

Academic Partners

Fraunhofer IZM - Germany
KAIST - South Korea

Participating Companies

Attendees at first workshop (March 10-11, 2008):

Air Products and Chemicals • ASE Group • ASM Technology • Atotech USA • AVX • Bosch GmbH • Brewer Science • CEA LETI Minatec • Endicott Interconnect Technologies • ETRI • EV Group • Fairchild Semiconductor • Fraunhofer IZM • Fujitsu Microelectronics America • Hynix Semiconductor • Ibiden • IBM • Indium Corporation of America • Intel • Jacket Micro Devices • KAIST • Kawasaki Microelectronics America • KEMET Electronics • Maxtek • Micron Technology • Murata Electronics • Nagase America Corp. • NASA Marshall Space Flight Center • NGK-NTK • nGiMat Co. • Nitto Americas • NXP Semiconductors • Panasonic • Qualcomm • Rambus Inc. • Rockwell Collins • Rohm & Haas • Rogers Corporation • SAMEER • Samsung Electronics • Scientific-Atlanta/Cisco • Sematech • Shanta Systems, Inc. • Shinko Electric Industries • Sonoscan • STATSChipPAC • ST Microelectronics • Surface Technology Systems (STS) • TechSearch International • Tektronix • Texas Instruments • U.S. Dept. of Defense • Vicor Corporation