Prof. Rao Tummala
PRC Director

GEORGIA TECH PRC ANNOUNCES RESEARCH HIGHLIGHTS IN ITS MOORE'S LAW FOR SYSTEMS RESEARCH

In contrast to the well-known Moore's Law for transistor integration in ICs, which brought the industry to a $2T IT industry over the last 5 decades, and encompasses hardware, software, services and applications, Georgia Tech PRC believes that similar progress must be made in component integration to achieve highest functionality in smallest size at lowest cost at system level. This is referred to as Moore's Law for Systems. Such a vision is being pioneered by Georgia Tech PRC, leading to entire systems on a little package (SOP). This vision, depicted below, includes eight core technologies such as 1) thin film passives, 2) ultra-thin actives, 3) system interconnections, 4) thermal interfaces and structures, 5) nanoscale materials, 6) mixed signal design and test, 7) mechanical design and reliability, and 8) power sources. Today, the PRC involves about 20 academic and research faculty and about 100 grad students In performing leading-edge device and systems packaging R&D in eight core research areas. Currently, the PRC is collaborating with about 70 companies from the US, Japan, Europe, Korea and India.

This issue features recent research highlights at GT PRC in the core research areas for:

Interconnections

• Chip-Last
• Low Temperature Cu-to-Cu
• Silicon Interposer to Organic Board

• Nano Magnetic
• High Density Capacitors
• Miniaturized RF Components

Silicon, Glass and Organic Substrates

• TSV Reliability
• Interposers for High-Bandwidth Applications
• Glass Package with 50µm Pitch
• Low-Cost Silicon Interposer

Thermal Technologies

Dr. Raj Pulugurtha
Program Manager

Prof. Rao Tummala
PRC Director

GEORGIA TECH PRC ANNOUNCES THIN FILM PASSIVE COMPONENTS (TPC) CONSORTIUM

for analog, digital, power and RF functions in partnership with Global Companies

March 3, 2011

The Georgia Tech Packaging Research Center, invites companies to join its new Global Industry R&D Consortium in Thin Film Passive Components (TPC). Research will concentrate on thin film passive components for analog, digital, power and RF functions in smart mobile electronics and implantable bio-electronic systems.

The focus of the consortium will be on: a) micro and nanoscale high-density and low-loss capacitors and inductors as surface thin film passives on silicon or glass with Through-Package Vias (TPVs) depicted in Fig. 1, b) digital and RF passives as thin film Integrated Passive Devices (IPDs) with high-permittivity and permeability dielectrics and noise isolation structures (Fig. 2). These thin IPDs can then be embedded into the package (Fig. 3) to realize total system miniaturization with improved performance.

Fig. 1 Power Components	Fig. 2 Digital and RF Components	Fig. 3 Interposer with Embedded Thin Film IPDs and Thin Film Passives

Unique feature of this Global Consortium include:

1. Power supply components with 10-100X enhancement in component volumetric efficiency
2. Enhanced film properties for lower loss and improved efficiency
3. Power integrity in high-speed processors and 3D ICs
4. Integrated energy storage in packages
5. Stable dielectrics with high permittivity and permeability at high frequencies
6. Tunable thin film components
7. Noise isolation in mixed-signal systems
   
   

Companies interested in joining the Thin Film Passive Components (TPC) Consortium are encouraged to contact Dr. Raj Pulugurtha at raj.puluturtha@prc.gatech.edu or Prof. Rao Tummala at rao.tummala@ece.gatech.edu.

Dr. Venky Sundaram
Program Manager

Prof. Rao Tummala
PRC Director

GT PRC EMBARKS ON ULTRA-THIN GLASS INTERPOSERS

at 10x lower cost than wafer-based silicon interposers in partnership with Global companies

February 28, 2011

Silicon interposers are being developed widely around the globe, as organic interposers reach their limits in I/Os, thermal dissipation, mechanical stress and warpage due to the large TCE mismatch between silicon devices and organic interposers. Most of these developments take advantage of existing and depreciated 200 and 300mm wafer fabs, using BEOL tools and processes as well as the newly-developed TSV technology for 3D ICs.

Georgia Tech PRC believes such silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers. Such an approach, therefore, may also be too expensive for many consumer and smart phone electronics. This is due primarily to four reasons:

1. Wafer-based approach results in small number of interposers; some of which may be as large as 30-50mm, thus driving up the cost of each
2. BEOL tools and processes are expensive for packaging applications
3. The TSV process uses DRIE and long-cycle time copper plating
4. The TSV requires insulating liner such as SiO2 that adds extra cost.
   
   

Georgia Tech PRC has undertaken a radically-different approach using ultra-thin glass panels yielding a larger number of interposers with lower-cost through-package-vias (TPV), towards a goal of 10x higher I/Os than organics and 10X lower cost than wafer-based silicon interposers. Glass interposer R&D advances include:

1. Thin glass formation without the need for chem-mech polish for an ultimate potential of 30µm thin panels that are as large as 700mm in size
2. Ultra-small via holes at ultra-fine pitch, comparable to TSV dimensions, at one-tenth the cost
3. Low-cost TPVs in glass without the need for an insulating liner, as required for TSV in silicon
4. Low-cost, double-side RDL materials and processes
5. Enhancement of thermal dissipation much beyond organics, similar to silicon interposers
6. Board level interconnection reliability of glass interposers to PWBs.
   
   

This technology is under development at Georgia Tech PRC with a large research team, in partnership with more than 15 global companies from the US, Japan, and Europe, as part of its Silicon and Glass Interposer Industry (SiGI) Consortium. The team has already demonstrated one of the first 50µm pitch TPVs in thin glass, as recognized by two IEEE best paper awards in 2010. Georgia Tech hopes to develop this exciting technology to demonstrate highest I/O density at lowest cost, in smallest size and at high frequencies to become the new de-facto standard interposer technology for future electronics.

Companies interested in joining the glass interposer research program within the SiGI Consortium are encouraged to contact Dr. Venky Sundaram at vs24@mail.gatech.edu, or Prof. Rao Tummala at rao.tummala@ece.gatech.edu.

PROF. RAO R. TUMMALA, GEORGIA TECH’S PACKAGING RESEARCH CENTER DIRECTOR, TO RECEIVE 2011 IEEE FIELD AWARD

His Integrated Approach to Research, Education and Industry Innovations and Collaborations Revolutionized Electronics Packaging Field

December 8, 2010

Rao R. Tummala, a pioneering, visionary researcher and educator who has made seminal contributions to microelectronics packaging and whose educational efforts have defined the field, is being honored by IEEE with the 2011 IEEE Field Award in Components, Packaging and Manufacturing Technologies. IEEE is the world’s largest technical professional association.

The award recognizes Tummala for pioneering, innovative and leadership contributions to industry’s first plasma display, multi-chip modules (MCM) and entire systems on a small package (SOP), cross-disciplinary education of more than 700 Ph.D, MS and BS students and globalization of electronic packaging by IEEE Society’s chapters and conferences and by global collaborations with more than 150 companies in the US, Japan, Korea and Europe. The award will be presented on 2 June 2011 at the IEEE Electronic Components and Technology Conference in Lake Buena Vista, Florida.

Electronics packaging deals with interconnecting, powering, cooling and protecting integrated circuits at device level without which Moore’s Law cannot be implemented into products. Going beyond Moore’s Law for ICs, he created the concept of Moore’s Law for system integration. Two paths have emerged over the last 3 decades for high performance computing and consumer systems—on-chip integration by system-on-chip and package integration by 2D and 3D multichip modules.

Tummala’s pioneering research began with 2D package integration with as many as 100 devices on a single module during his 25-year career at IBM with pioneering inventions in the first and next three generations of multichip packaging based on ceramics and polymer-copper thin-film interconnections. His Low-Temperature, Co-fired Ceramic (LTCC) technology, a standard in the industry today, resulted in the first 100-chip multichip module. After moving to the Georgia Institute of Technology, Atlanta, Ga., Tummala introduced the SOP concept, as Moore’s Law for System Integration, exploring, demonstrating and integrating entire system functions in a little package with passives, power, thermal, and power components. His SOP vision is to create mega-functional systems in smallest size at lowest cost.

At Georgia Tech, Tummala provided leadership in making packaging an “academic subject” by means of courses, curricula, textbooks and degrees.” His proposal to the National Science Foundation in 1993 resulted in the establishment of first NSF Engineering Research Center in US, at Georgia Tech, demonstrating for the first time an integrated and comprehensive approach to leading-edge research, cross-disciplinary education and global industry collaborations and technology transfer programs–all in SOP. He has also authored several reference and textbooks books that shaped the modern packaging landscape. Considered the “Bible of Packaging,” his Microelectronics Packaging Handbook (Van Nostrand Reinhold, 1989) defined packaging for the first time and introduced its cross-disciplinary nature of science and technology to the academic community. He authored the first undergraduate textbook, now used by more than 100 universities in the US, Europe, China, Japan and Korea. As president of the IEEE Components, Packaging and Manufacturing Technology Society from 2001 to 2004, Tummala was instrumental in broadening the Society’s global reach.

An IEEE Fellow and IBM Fellow, Tummala is also a member of National Academy of Engineering. He received 16 Technical Innovation Awards and nine Invention Awards from IBM. Other awards include the IEEE David Sarnoff Award, IEEE Third Millennium Medal and IEEE Major Education Medal. He obtained a bachelor’s degree in metallurgy from the Indian Institute of Science, Bangalore, and a doctorate in materials science and engineering from the University of Illinois, Urbana. Tummala is currently an endowed chair professor and director of the 3D Systems Packaging Research Center at the Georgia Institute of Technology.