PICS 2018

Package Integration at Chip and System Levels (PICS) for Next Generation Consumer, Computing, Communication, Biomedical, and Automotive Electronics – November 7-9, 2018 – Atlanta, GA


As the end of Moore’s law begins to emerge for simultaneous improvements in transistor density and cost, packaging is expected to save the day at the semiconductor and system industries. Such a scenario requires both homogeneous and heterogeneous package integration at IC level by 2D, 2.5D and 3D in the short term, and most importantly, at system level by integration of not only active ICs but also passive RF, Power and thermal components. Whereas a good current example of the former is 2.5D Si interposers for logic-to memory bandwidth, a single package smartphone is an example of the latter. While the current package integration technologies such as Si interposers serve today’s needs, more cost-effective technologies such as panel and roll to roll using ultra-thin laminate and glass packaging along with advances in ultra-thin polymer dielectrics, large area tools and processes are necessary with much higher throughput so as to make PICS more pervasive in applications that range from, not only cloud computing but also in consumer, communication, IOT, wearable, implantable and high power, high temperature automotive electronics. Such a need presents unparalleled research, development, manufacturing, education and marketing opportunities. New paradigms in device-package-system architectures beyond the current 2.5D and 3D enabled by advances in materials, tools, processes, substrates, components and integrated functions need to be explored in R&D and in manufacturing. Georgia Tech sees unprecedented technical challenges and opportunities in electrical, mechanical, optical and thermal designs, and new digital, RF, millimeter wave, sensing, high-power and high-temp, and flexible and wearable electronics.

Workshop Sessions

  1. Plenary Keynote Sessions
    Global leaders from industry and academia will present their perspective on topics related to Heterogenous Integration.
  2. Heterogenous integration for mobile, edge and cloud computing, IoT, data centers, autonomous driving, and cognitive systems.
  3. Heterogenous integration for smartphone, small- or pico-cell, autonomous driving, radar, IoT, and sensing networks.
  4. Heterogenous integration for High-power, High-temperature, and High-reliability for highly-efficient but ultra-miniaturized power modules for electric vehicles.
  5. Heterogenous integration for ultra-thin and integrated flexible and wearable packaging for implantable, wearable, or contoured electronics.
  6. Interactive Student Poster Session from Global Universities
    Grad students from universities and technical institutes performing leading-edge R&D across the globe will present technical poster papers related to the workshop themes in Heterogenous Integration.

Who Should Attend

Design, R&D and manufacturing leaders across the entire supply-chain – including semiconductor, package, assembly, components, and end users in various markets including mobile, AI, cloud, IoT, power, autonomous driving and electric cars, and medical.


For more information, please contact:
Ms. Karen May, Workshop Coordinator
Georgia Institute of Technology
813 Ferst Drive, NW
Atlanta, GA 30332  USA
+1 404 385-1220


This event will be held at: 
Georgia Tech Global Learning Center
84 5th St. NW
Atlanta, GA 30308-1031
Tel: 404 385-6203
Atlanta, GA 30332  USA