PRESENTATIONS

Plenary Keynote Session

8:05AM - 8:15AM
Welcome & Introduction
Prof. Rao R. Tummala, Director, NSF-ERC, Georgia Institute of Technology

8:15 - 9:00
System-on-Chip (SOC): Status and Challenges
Mahesh Mehendale, TI Fellow, Texas Instruments, India

9:00 - 9:45
Realizing Effective SOCs with Viable 3D Interconnect
Dr. H. Bernhard Pogge, IBM Fellow, IBM Microelectronics  

9:45 - 10:30
System-in-Package (SIP): Status and Challenges
Ken Brown, Manager, Non-CPU Packaging, Intel , USA

11:00 - 11:45
Wafer Level SIP
Peiter Hooijmans, Vice President, RF Program Manager, Phillips  

11:45 - 12:30
System-in-Package Roadmap
Joe Adam, Vice President, SkyWorks , USA

1:30 - 2:15
System-on-Package (SOP)
Rao Tummala, Director, NSF-ERC, Georgia Institute of Technology  

Technical Sessions

Thursday, September 22, 2005

Session 1: Mixed Signal Design
Chairs: Prof. Madhavan Swaminathan, Deputy Director, NSF-ERC, Packaging Research Center - Georgia Institute of Technology & Dr. Grit Sommer, Infineon , Germany

2:15PM-2:40PM
Electromagnetic Band Gap Technology for Noise Mitigation - Prof. Omar M. Ramahi, University of Maryland  

2:40-3:05
Mixed Signal Research for Digital Convergence - Madhaven Swaminathan, Deputy Director, Packaging Research Center - Georgia Institute of Technology

Session 2: Optical System-on-Package (SOP)
Chairs: Prof .G.K. Chang, Associate Director, Packaging Research Center - Georgia Institute of Technology & Prof. Ray Chen University of Texas

3:30PM-3:55PM
Optoelectronics System-in-Package (SIP) on Silicon Platform - Dr. Christine Louis, LETI in France

3:55-4:20
Optical Interconnects Technologies on High-Speed Backplanes - Alexei L. Glebov, Michael G. Lee and Kishio Yokouchi, Fujitsu Laboratories of America.

4:20-4:45
Chip-to-Chip Optoelectronics with Embedded Components - Dr. Ray Chen, Microelectronics Research Center, University of Texas - Austin

Session 3: RF System-on-Package (SOP)
Chairs: Manos Tentzeris, Associate Director, Packaging Research Center - Georgia Institute of Technology

4:45PM-5:10PM
Wafer-Level Packaging for RF Applications Using Low-Loss Spacer Substrate for Integration of Passives - S. Sinaga, A. Polyakov, M. Bartek, Delft University of Technology

5:10-5:35
RF/Digital LTCC Module Using Embedded Decoupling Capacitor and Wide Bandpass Filter - Y. H. Park, K. J. Oh, Y. K. Lee, Samsung Electro-mechanics Co., Ltd.; B. S. Kim, Sungkyunkwan University

5:35-6:00
RF SOP with Embedded Components - Prof. Manos Tentzeris, Associate Director, Packaging Research Center - Georgia Institute of Technology

Friday, September 23, 2005

8:05AM - 8:15AM
Welcome & Introduction - Rao R. Tummala, PRC Director

Session 4: Wafer Level Packaging for System-in-Package (SIP) and System-on-Package (SOP)
Chairs: Prof. C. P. Wong, Associate Director, Packaging Research Center - Georgia Institute of Technology & Dr. Luu Nguyen, National Semiconductor  

8:15-8:40
Novel WLP through Silicon Vias for Chip Level 3D Integration - Mitsuo Umemoto, Sanyo Electric Co., Ltd. Semiconductor Company

8:40-9:05
Innovative Flip Chip Solution for System-On-Wafer Concept - N. Sillon, J. C. Souriau, J. Brun, CEA Leti, France  

9:05-9:30
Electromigration in Lead-Free Wafer Level Packages - Dr. Luu Nguyen, National Semiconductor

9:30-9:55
Photo-Definable Nanocomposite for Wafer Level Packaging - C. P. Wong, Packaging Research Center - Georgia Institute of Technology  

Session 5: Mixed Signal Electrical Test
Chairs: Prof. Abhijit Chatterjee, Packaging Research Center - Georgia Institute of Technology

10:15-10:40
Test Challenges for 3D Circuits – T.M. Mak, Intel

10:40-11:05
Low Cost Test of Embedded RF Modules - S. Bhattacharya, A. Chatterjee, School of Electrical and Computer Engineering, Georgia Institute of Technology

11:05-11:30
Ultra High-Speed Wafer-Level Testing of SOPs - A. M. Majid, D. C. Keezer, School of Electrical and Computer Engineering, Georgia Institute of Technology

Session 6: Embedded Actives and Passives
Chairs: Dr. Mahadevan Iyer, IME, Singapore and Venky Sundaram, Packaging Research Center, Georgia Institute of Technology

12:30-12:55
System-on-Package (SOP) Functional Integration in Power Electronics Module Using a Planar Technology - Zhenxian Liang, Research Assistant Professor, Center for Power Electronics System (CPES) Virginia Polytechnic Institute and State University

12:55-1:20
Liquid Crystalline Polymer Substrates for Multi-band Wireless and Mixed Signal Module - George White, CTO, Jacket Micro Devices  

1:20-1:45
Chips First Build-Up for SOP/SIP Applications - Raymond A. Fillion, GE Global Research Center

1:45-2:10
Development of a New Interposer Including Embedded Film Passive Elements for SOP/SIP Application - Toshiaki Mori, Satoru Juramoti, Kousuke Suzuki, Dai Nippon Priting Co., Ltd.; Yoshitaka Fukuoka, Weisti Ltd.

Session 7: Novel System-on-Package (SOP) and Applications
Chairs: Joe Adam, Vice President, SkyWorks & George Conner, Phillips  

2:25-2:50
Towards 3D in-Mould Assembly of Electronics into Mechanics - Pia Tanskanen, Pekka Laukkala, Nokia Research Center , Finland

2:50-3:15
Hybrid Fuel Cell / Lithium-Ion Powered, Power-Conscious SIP ICs - G. A. Rincón-Mora, Chairman, IEE E Atlanta SSCS-CAS Chapter, Analog and Power IC Design Lab, Georgia Institute of Technology

3:15-3:40
Board and Package Level Thermal Design Optimization of Stacked-Die Packages for Handheld Applications - Sung-won Moon, Chia-pin Chiu, and Suzana Prstic, Intel Corp.

3:40-4:05
Ultra-thin Silicon µ-via Substrates and Integrated µ-vias for SiP Applications - Andreas Hase, Jochen Kuhmann, Lior Shiv, Matthias Heschel, Hilmar Korth, Frank Mueller and Steen Weichl, Hymite, GmbH

Session 8: Panel Discussion, Topic: SOP vs. SIP vs. SOC
Chair: Rao Tummala, Director NSF-ERC, Packaging Research Center, Georgia Institute of Technology

4:05-5:30
SOC - Mahesh Mehendale, TI Fellow, Texas Instruments & Dr. H. Bernhard Pogge, IBM Fellow, IBM Microelectronics
SIP - Joe Adam, Vice President, Sky Works & George Conner, Phillips & Peiter Hooijmans, Vice President, RF Program Manager, Phillips
SOP in Organics vs. Ceramics - Madhavan Swaminathan, Deputy Director, Packaging Research Center - Georgia Institute of Technology

5:30-5:40 Closing Comments - Rao Tummala, Director, Packaging Research Center, Georgia Institute of Technology

www.prc.gatech.edU/3s

First 3S a Great Success!

The Georgia Institute of Technology Microsystems Packaging Research Center (PRC) recently hosted the First International Workshop on 3S (SOP, SIP, SOC) Electronic Technologies. The workshop was held in Atlanta Georgia September 22 & 23, 2005 and was co-sponsored by IEEE and the PRC. The event featured speakers and attendees from over 40 global companies, national research institutions, and top-tier universities. Discussions on state-of-the-art microelectronic technologies, trends, and challenges were presented by leaders in the packaging industry. The two day session culminated with a panel discussion on the distinction and direction for the often complimentary SOP, SIP and SOC technologies. This workshop generated great interest from the global microelectronics industry and expectations are high for the 2nd 3S workshop, currently planned for Sept. 21-22, 2006. For further information regarding the next 3S workshop contact Boyd Wiedenman (boyd.wiedenman@ece.gatech.edu)