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September 28 & 29, 2006 Global Learning & Conference Center at Technology Square 84 Fifth Street, Atlanta, GA 30308 U.S.A. Meeting Rooms: Auditorium 222, View GLCC floor plan, 2nd floor. Click for Georgia Tech Area Hotels General Chair: Rao Tummala, Director, Georgia Institute of Technology (rao.tummala@ee.gatech.edu) Technical Chairs: Dr. Mahadevan Iyer Program Administrator: Boyd Wiedenman boyd.wiedenman@ece.gatech.edu Download FINAL PROGRAM (pdf, 1.4mb)

The first workshop, held at Georgia Tech in September 2005, was highly successful with industry keynote talks from TI, IBM , Intel, Philips and Skyworks. More than 80 people attended the workshop from Japan , Korea , Europe and the U.S. (View report and presentations from First 3S workshop)

The focus of the second workshop will explore current trends and state-of-the-art “3S” technologies and applications of “on-chip” SOC , “on-module” SIP and “on–system” SOP. Electronics package integration is taking place by means of either on-wafer or on-ceramic LTCC or organic laminate technologies. The tradeoffs between these are also of interest. This workshop will review the latest design, R & D and manufacturing status as well as applications of each of the three electronic packaging technologies currently being used around the world. It will also attempt to compare and contrast SOC , 3D stacking, SIP, SOP and MCM as related to distinct application sectors.

The SOP Paradigm: SOP is emerging around the globe particularly in Japan as it changes the current chip-centric SOC methodology to a cheaper, faster-to-market IC-package-system co-design flow. The advantages of the SOP paradigm over SOC appear overwhelming due to SOP’s design simplicity, lower cost and higher system function integration, electrical performance, without the intellectual property issues that dominate SOC . The SOP is also different from, yet complimentary to, 3D packaging and SIP. The SOP goes one step further in the ultimate 3D integration of components in thin film form at microscale, in the short term, and nanoscale in the long term. The SOP focuses on integrating both single function as well as heterogeneous system functions, optimizing ICs for transistors and package for integration of digital, RF, optical, sensor and others. It accomplishes this by build-up SOP, similar to ICs and stacked SOP, and is similar to parallel board fabrication. To summarize, this workshop will review the latest design, R & D and manufacturing status as well as applications of each of the three electronic packaging technologies currently being used around the world. It will also attempt to compare and contrast SOC, 3D stacking, SIP, SOP and MCM.

3S Technologies & Applications in:
Automotive, Computing, Consumer & Wireless, Military & Defense, & Bio-Medical Systems

SOC / SIP / SOP Topics on:
Design, Materials, Fabrication, Assembly, and Process Technologies

Specific Topics:

• Mixed Signal Design and Design Tools
• Embedded Digital Integration and Modules
• Multifunction Integration and Modules
• 3D Stacked ICs and Packages
• Embedded Passives
• Bio SIP
• Embedded RF Integration and Modules
• Materials, Processes, Fabrication and Assembly
• Embedded Optical integration and Modules
• High Density Interconnects, HDI Core and Coreless Substrates
• Bio Wireless Sensing
• Mixed Signal Test
• Mixed Signal Reliability